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1. 发明申请

US20060130743A1 Low temperature load and bake 有权
公开(公告)号：US20060130743A1
公开(公告)日：2006-06-22
申请号：US11352738
申请日：2006-02-10
申请人： Paul Brabant , Joe Italiano , Jianqing Wen
发明人： Paul Brabant , Joe Italiano , Jianqing Wen
IPC分类号： C30B23/00 , C30B25/00 , C30B28/14 , C30B11/00 , C30B28/12
CPC分类号： C23C16/4408 , C23C16/0209 , C23C16/0227 , C23C16/4405 , C30B25/02 , C30B25/18 , C30B29/30 , C30B31/00 , H01L21/02046 , H01L21/02052 , Y10T117/10 , Y10T117/1004 , Y10T117/1008
摘要： Methods are provided for low temperature, rapid baking to remove impurities from a semiconductor surface prior to in-situ deposition. Advantageously, a short, low temperature process consumes very little of the thermal budget, such that the process is suitable for advanced, high density circuits with shallow junctions. Furthermore, throughput is greatly improved by the low temperature bake, particularly in combination with low temperature plasma cleaning and low temperature wafer loading prior to the bake, and deposition after the bake at temperatures lower than conventional epitaxial deposition. The process enables epitaxial deposition of silicon-containing layers over semiconductor surfaces, particularly enabling epitaxial deposition over a silicon germanium base layer. By use of a low-temperature bake, the silicon germanium base layer can be cleaned to facilitate further epitaxial deposition without relaxing the strained crystal structure of the silicon germanium.

2. 发明申请

US20050026400A1 Methods for depositing amorphous materials and using them as templates for epitaxial films by solid phase epitaxy 有权
标题翻译：用于沉积非晶材料并将其用作通过固相外延的外延膜的模板的方法
公开(公告)号：US20050026400A1
公开(公告)日：2005-02-03
申请号：US10871687
申请日：2004-06-09
申请人： Michael Todd , Paul Brabant , Keith Weeks , Jianqing Wen
发明人： Michael Todd , Paul Brabant , Keith Weeks , Jianqing Wen
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： H01L21/02667 , H01L21/02634 , H01L21/2022
摘要： Methods for forming epitaxial films involve forming a buffer layer on a single crystal substrate, depositing an amorphous layer on the buffer layer, then forming an epitaxial film from the amorphous layer by solid phase epitaxy.
摘要翻译：用于形成外延膜的方法包括在单晶衬底上形成缓冲层，在缓冲层上沉积非晶层，然后通过固相外延从非晶层形成外延膜。

3. 发明授权

US07837795B2 Low temperature load and bake 有权
标题翻译：低温负荷和烘烤
公开(公告)号：US07837795B2
公开(公告)日：2010-11-23
申请号：US11352738
申请日：2006-02-10
申请人： Paul D. Brabant , Joe P. Italiano , Jianqing Wen
发明人： Paul D. Brabant , Joe P. Italiano , Jianqing Wen
IPC分类号： C30B21/02
CPC分类号： C23C16/4408 , C23C16/0209 , C23C16/0227 , C23C16/4405 , C30B25/02 , C30B25/18 , C30B29/30 , C30B31/00 , H01L21/02046 , H01L21/02052 , Y10T117/10 , Y10T117/1004 , Y10T117/1008
摘要： Methods are provided for low temperature, rapid baking to remove impurities from a semiconductor surface prior to in-situ deposition. Advantageously, a short, low temperature process consumes very little of the thermal budget, such that the process is suitable for advanced, high density circuits with shallow junctions. Furthermore, throughput is greatly improved by the low temperature bake, particularly in combination with low temperature plasma cleaning and low temperature wafer loading prior to the bake, and deposition after the bake at temperatures lower than conventional epitaxial deposition. The process enables epitaxial deposition of silicon-containing layers over semiconductor surfaces, particularly enabling epitaxial deposition over a silicon germanium base layer. By use of a low-temperature bake, the silicon germanium base layer can be cleaned to facilitate further epitaxial deposition without relaxing the strained crystal structure of the silicon germanium.
摘要翻译：提供了用于低温，快速烘烤以在原位沉积之前从半导体表面去除杂质的方法。有利地，短的低温工艺消耗很少的热预算，使得该工艺适用于具有浅结的先进的高密度电路。此外，通过低温烘烤，特别是结合烘烤前的低温等离子体清洗和低温晶片负载以及在低于常规外延沉积的温度下烘烤后沉积，可以大大提高产量。该方法能够在半导体表面上外延沉积含硅层，特别是能够在硅锗基底层上进行外延沉积。通过使用低温烘烤，可以清洁硅锗基底层以促进进一步的外延沉积，而不会松弛硅锗的应变晶体结构。

4. 发明授权

US07108748B2 Low temperature load and bake 有权
公开(公告)号：US07108748B2
公开(公告)日：2006-09-19
申请号：US10158393
申请日：2002-05-29
申请人： Paul D. Brabant , Joe P. Italiano , Jianqing Wen
发明人： Paul D. Brabant , Joe P. Italiano , Jianqing Wen
IPC分类号： C60B25/10
CPC分类号： C23C16/4408 , C23C16/0209 , C23C16/0227 , C23C16/4405 , C30B25/02 , C30B25/18 , C30B29/30 , C30B31/00 , H01L21/02046 , H01L21/02052 , Y10T117/10 , Y10T117/1004 , Y10T117/1008
摘要： Methods are provided for low temperature, rapid baking to remove impurities from a semiconductor surface prior to in-situ deposition. Advantageously, a short, low temperature process consumes very little of the thermal budget, such that the process is suitable for advanced, high density circuits with shallow junctions. Furthermore, throughput is greatly improved by the low temperature bake, particularly in combination with low temperature plasma cleaning and low temperature wafer loading prior to the bake, and deposition after the bake at temperatures lower than conventional epitaxial deposition. The process enables epitaxial deposition of silicon-containing layers over semiconductor surfaces, particularly enabling epitaxial deposition over a silicon germanium base layer. By use of a low-temperature bake, the silicon germanium base layer can be cleaned to facilitate further epitaxial deposition without relaxing the strained crystal structure of the silicon germanium.

5. 发明申请

US20080026149A1 METHODS AND SYSTEMS FOR SELECTIVELY DEPOSITING SI-CONTAINING FILMS USING CHLOROPOLYSILANES 审中-公开
标题翻译：使用氯代石蜡选择性沉淀含SI膜的方法和系统
公开(公告)号：US20080026149A1
公开(公告)日：2008-01-31
申请号：US11753370
申请日：2007-05-24
申请人： Pierre Tomasini , Chantal Arena , Matthias Bauer , Nyles Cody , Ronald Bertram , Jianqing Wen , Matthew Stephens
发明人： Pierre Tomasini , Chantal Arena , Matthias Bauer , Nyles Cody , Ronald Bertram , Jianqing Wen , Matthew Stephens
IPC分类号： C23C16/00
CPC分类号： H01L21/28518 , C23C16/04 , C23C16/24 , C30B25/02 , C30B25/18 , C30B29/06 , H01L21/02381 , H01L21/02529 , H01L21/02532 , H01L21/02576 , H01L21/02579 , H01L21/0262 , H01L21/02639
摘要： Chloropolysilanes are utilized in methods and systems for selectively depositing thin films useful for the fabrication of various devices such as microelectronic and/or microelectromechanical systems (MEMS).
摘要翻译：氯多硅烷用于选择性沉积薄膜的方法和系统中，薄膜可用于制造诸如微电子和/或微机电系统（MEMS）的各种装置。

6. 发明申请

US20060201414A1 Low temperature load and bake 有权
公开(公告)号：US20060201414A1
公开(公告)日：2006-09-14
申请号：US11433535
申请日：2006-05-12
申请人： Paul Brabant , Joe Italiano , Jianqing Wen
发明人： Paul Brabant , Joe Italiano , Jianqing Wen
IPC分类号： C30B23/00 , C30B25/00 , C30B28/12 , C30B28/14
CPC分类号： C23C16/4408 , C23C16/0209 , C23C16/0227 , C23C16/4405 , C30B25/02 , C30B25/18 , C30B29/30 , C30B31/00 , H01L21/02046 , H01L21/02052 , Y10T117/10 , Y10T117/1004 , Y10T117/1008
摘要： Methods are provided for low temperature, rapid baking to remove impurities from a semiconductor surface prior to in-situ deposition. Advantageously, a short, low temperature process consumes very little of the thermal budget, such that the process is suitable for advanced, high density circuits with shallow junctions. Furthermore, throughput is greatly improved by the low temperature bake, particularly in combination with low temperature plasma cleaning and low temperature wafer loading prior to the bake, and deposition after the bake at temperatures lower than conventional epitaxial deposition. The process enables epitaxial deposition of silicon-containing layers over semiconductor surfaces, particularly enabling epitaxial deposition over a silicon germanium base layer. By use of a low-temperature bake, the silicon germanium base layer can be cleaned to facilitate further epitaxial deposition without relaxing the strained crystal structure of the silicon germanium.

7. 发明授权

US07462239B2 Low temperature load and bake 有权
标题翻译：低温负荷和烘烤
公开(公告)号：US07462239B2
公开(公告)日：2008-12-09
申请号：US11433535
申请日：2006-05-12
申请人： Paul D. Brabant , Joe P. Italiano , Jianqing Wen
发明人： Paul D. Brabant , Joe P. Italiano , Jianqing Wen
IPC分类号： C30B25/10
CPC分类号： C23C16/4408 , C23C16/0209 , C23C16/0227 , C23C16/4405 , C30B25/02 , C30B25/18 , C30B29/30 , C30B31/00 , H01L21/02046 , H01L21/02052 , Y10T117/10 , Y10T117/1004 , Y10T117/1008
摘要： Methods are provided for low temperature, rapid baking to remove impurities from a semiconductor surface prior to in-situ deposition. Advantageously, a short, low temperature process consumes very little of the thermal budget, such that the process is suitable for advanced, high density circuits with shallow junctions. Furthermore, throughput is greatly improved by the low temperature bake, particularly in combination with low temperature plasma cleaning and low temperature wafer loading prior to the bake, and deposition after the bake at temperatures lower than conventional epitaxial deposition. The process enables epitaxial deposition of silicon-containing layers over semiconductor surfaces, particularly enabling epitaxial deposition over a silicon germanium base layer. By use of a low-temperature bake, the silicon germanium base layer can be cleaned to facilitate further epitaxial deposition without relaxing the strained crystal structure of the silicon germanium.
摘要翻译：提供了用于低温，快速烘烤以在原位沉积之前从半导体表面去除杂质的方法。有利地，短的低温工艺消耗很少的热预算，使得该工艺适用于具有浅结的先进的高密度电路。此外，通过低温烘烤，特别是结合烘烤前的低温等离子体清洗和低温晶片负载以及在低于常规外延沉积的温度下烘烤后沉积，可以大大提高产量。该方法能够在半导体表面上外延沉积含硅层，特别是能够在硅锗基底层上进行外延沉积。通过使用低温烘烤，可以清洁硅锗基底层以促进进一步的外延沉积，而不会松弛硅锗的应变晶体结构。

8. 发明授权

US07029995B2 Methods for depositing amorphous materials and using them as templates for epitaxial films by solid phase epitaxy 有权
标题翻译：用于沉积非晶材料并将其用作通过固相外延的外延膜的模板的方法
公开(公告)号：US07029995B2
公开(公告)日：2006-04-18
申请号：US10871687
申请日：2004-06-09
申请人： Michael A. Todd , Paul D. Brabant , Keith D. Weeks , Jianqing Wen
发明人： Michael A. Todd , Paul D. Brabant , Keith D. Weeks , Jianqing Wen
IPC分类号： H01L21/20
CPC分类号： H01L21/02667 , H01L21/02634 , H01L21/2022
摘要： Methods for forming epitaxial films involve forming a buffer layer on a single crystal substrate, depositing an amorphous layer on the buffer layer, then forming an epitaxial film from the amorphous layer by solid phase epitaxy.
摘要翻译：用于形成外延膜的方法包括在单晶衬底上形成缓冲层，在缓冲层上沉积非晶层，然后通过固相外延从非晶层形成外延膜。

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