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1. 发明授权

US07484031B2 Bus connection device 有权
标题翻译：总线连接装置
公开(公告)号：US07484031B2
公开(公告)日：2009-01-27
申请号：US11628129
申请日：2005-05-24
申请人： Jerome Tjia
发明人： Jerome Tjia
IPC分类号： G06F13/20 , G06F13/36 , G06F13/38 , G06F13/40
CPC分类号： G06F13/4027 , G06F2213/0042
摘要： A bus connection device, in the form of a hardware dongle, can be connected to a first electronic device, in the form of a USB peripheral device, and a second electronic device can be connected thereto. The dongle can determine whether the second connected device is a USB host device or a USB peripheral device and, if the second electronic device is a USB host device, it is connected directly to the first electronic device. If the second electronic device is a USB peripheral device, the bus connection device operates to allow the first electronic device to operate as a host device. When the bus connection device is operating to allow the first electronic device to act as a USB host device, it regularly sends tokens to the first electronic device and to the second electronic device, to which the first electronic device can respond by transmitting data intended for the second electronic device, and to which the second electronic device can respond by transmitting data intended for the first electronic device.
摘要翻译：以硬件加密狗形式的总线连接装置可以以USB外围设备的形式连接到第一电子设备，并且可以将第二电子设备连接到第一电子设备。加密狗可以确定第二个连接的设备是USB主机设备还是USB外围设备，如果第二个电子设备是USB主机设备，则它直接连接到第一个电子设备。如果第二电子设备是USB外围设备，则总线连接设备操作以允许第一电子设备作为主机设备操作。当总线连接装置正在操作以允许第一电子设备充当USB主机设备时，它定期向第一电子设备和第二电子设备发送令牌，第一电子设备可以通过发送用于第二电子设备，并且第二电子设备可以通过发送用于第一电子设备的数据来对其进行响应。

2. 发明授权

US07054975B2 Interrupt generation in a bus system 有权
标题翻译：总线系统中断产生
公开(公告)号：US07054975B2
公开(公告)日：2006-05-30
申请号：US10040180
申请日：2001-10-23
申请人： Jerome Tjia
发明人： Jerome Tjia
IPC分类号： G06F13/24
CPC分类号： G06F13/385
摘要： The present invention relates to a bus system comprising a first and second station (10, 14) coupled via a bus (12) for transferring data and control signals, the bus (12) operating according to a protocol in which the first station (10) repeatedly sends requests (200, 210, 220, 230) for data to the second station, the second station (14) responding to each request (200, 210, 220, 230) by sending a message with a data item or sending a negative acknowledge signal (24), wherein the second station (14) comprises: an interruptable processor (15) for generating data items; a first in first out buffer (160) coupled between the processor (15) and the bus (12), for buffering data items for successive messages in a first in first out order, the processor (15) being programmed to start writing the data items to the buffer (160) in response to an interrupt (204, 234); a bus interface (162) arranged to handle the protocol, sending data items from the buffer (160) in the messages, the bus interface (162) sending an interrupt to the processor (15) in response to selected ones of the requests (200, 210, 220, 230), when the buffer is empty and no interrupts have yet been generated since the processor has written into the buffer.
摘要翻译：本发明涉及一种总线系统，包括经由总线（12）耦合的用于传送数据和控制信号的第一和第二站（10,14），总线（12）根据其中第一站（10））重复地向第二站发送用于数据的请求（200,210,220,230），所述第二站（14）通过发送具有数据项的消息或发送数据项来响应每个请求（200,210,220,230）否定确认信号（24），其中所述第二站（14）包括：用于产生数据项的可中断处理器（15）; 耦合在处理器（15）和总线（12）之间的先出先出缓冲器（160），用于以先到先出的顺序缓冲连续消息的数据项，处理器（15）被编程为开始写数据响应于中断（204,234）到缓冲器（160）的项目; 布置成处理协议的总线接口（162），用于在消息中从缓冲器（160）发送数据项，总线接口（162）响应于所选择的请求（200）向处理器（15）发送中断，210,220,230），当缓冲器为空并且由于处理器已经写入到缓冲器中时，还没有产生中断。

3. 发明授权

US08396913B2 Fast fourier transform architecture 有权
标题翻译：快速傅立叶变换架构
公开(公告)号：US08396913B2
公开(公告)日：2013-03-12
申请号：US11911088
申请日：2006-04-11
申请人： Tianyan Pu , Lei Bi , Jerome Tjia
发明人： Tianyan Pu , Lei Bi , Jerome Tjia
IPC分类号： G06F17/14
CPC分类号： G06F17/142
摘要： A last fourier transform architecture has parallel data processing paths. Input data is applied to the parallel data processing paths in a repeating sequence, and processed in those paths. Data sequencers are used to combine the outputs from the data processing paths into the required sequence.
摘要翻译：最后一个傅立叶变换架构具有并行数据处理路径。输入数据以重复序列应用于并行数据处理路径，并以这些路径进行处理。数据定序器用于将来自数据处理路径的输出组合到所需的序列中。

4. 发明授权

US08269522B2 Active eye opener for current-source driven, high-speed serial links 有权
标题翻译：主动开眼机用于电流源驱动，高速串行链路
公开(公告)号：US08269522B2
公开(公告)日：2012-09-18
申请号：US12966480
申请日：2010-12-13
申请人： Charles Razzell , Hong Sair Lim , Batuhan Okur , Jerome Tjia , Tue Fatt David Wee
发明人： Charles Razzell , Hong Sair Lim , Batuhan Okur , Jerome Tjia , Tue Fatt David Wee
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H04B3/06 , H04L25/0282
摘要： A current boost circuit acts as an “eye opener” for a digital bus line. A controlled current injects a fraction of the normal signaling current magnitude from a source driver onto the bus line, after a transition between the two logical states on the bus line is detected. The duration of the additional current injection is a fraction of the unit interval. In one embodiment, a linear system uses the summation of a proportional boost current and a delayed and negated proportional boost current. In another embodiment, a positive or negative edge detection circuit triggers a monostable pulse generator that controls the injection of short bursts of additional current into the bus lines. In some embodiments the boost current is suppressed when the bus line is driven from a driver other than the source driver.
摘要翻译：电流升压电路充当数字总线的“开眼”。在检测到总线上的两个逻辑状态之间的转换之后，受控电流将来自源极驱动器的正常信号电流幅度的一部分注入到总线上。额外电流注入的持续时间是单位间隔的一小部分。在一个实施例中，线性系统使用比例升压电流和延迟和否定比例升压电流的总和。在另一个实施例中，正或负边缘检测电路触发单稳脉冲发生器，其控制向总线线路注入附加电流的短脉冲串。在一些实施例中，当总线从除源极驱动器之外的驱动器驱动时，升压电流被抑制。

5. 发明申请

US20100011043A1 FAST FOURIER TRANSFORM ARCHITECTURE 有权
标题翻译：快速FOURIER变形架构
公开(公告)号：US20100011043A1
公开(公告)日：2010-01-14
申请号：US11911088
申请日：2006-04-11
申请人： Tianya Pu , Lei Bi , Jerome Tjia
发明人： Tianya Pu , Lei Bi , Jerome Tjia
IPC分类号： G06F17/14
CPC分类号： G06F17/142
摘要： A last fourier transform architecture has parallel data processing paths. Input data is applied to the parallel data processing paths in a repeating sequence, and processed in those paths. Data sequencers are used to combine the outputs from the data processing paths into the required sequence.
摘要翻译：最后一个傅立叶变换架构具有并行数据处理路径。输入数据以重复序列应用于并行数据处理路径，并以这些路径进行处理。数据定序器用于将来自数据处理路径的输出组合到所需的序列中。

6. 发明申请

US20070152738A1 Pull-up circuit 有权
标题翻译：上拉电路
公开(公告)号：US20070152738A1
公开(公告)日：2007-07-05
申请号：US10597089
申请日：2004-12-29
申请人： Rick Stopel , Jerome Tjia
发明人： Rick Stopel , Jerome Tjia
IPC分类号： G05F1/10
CPC分类号： H04L25/0264 , G06F13/4072 , H03K19/01721
摘要： A pull-up circuit comprises an operational amplifier which forms part of a feedback circuit, acting to bring a pull-up circuit output equal to a reference voltage input. The pull-up circuit may form part of a USB transceiver for incorporation in a USB Device. When the supply voltage of the USB Device is sufficiently high, it is used to provide the required pull-up voltage, with the feedback circuit including the operational amplifier the USB Device is not high enough to provide the required pull-up voltage. In that case, the USB bus voltage is used to generate the reference voltage which is used as an input to the feedback circuit.
摘要翻译：上拉电路包括形成反馈电路的一部分的运算放大器，用于使上拉电路输出等于参考电压输入。上拉电路可以构成用于并入USB设备的USB收发器的一部分。当USB设备的电源电压足够高时，它被用于提供所需的上拉电压，反馈电路包括运算放大器，USB设备不足以提供所需的上拉电压。在这种情况下，USB总线电压用于产生用作反馈电路的输入的参考电压。

7. 发明授权

US08595725B2 Method and system for processing jobs with two dual-role devices 有权
标题翻译：用于处理具有两个双重角色设备的作业的方法和系统
公开(公告)号：US08595725B2
公开(公告)日：2013-11-26
申请号：US11596830
申请日：2005-05-20
申请人： Jerome Tjia , Zhenyu Zhang
发明人： Jerome Tjia , Zhenyu Zhang
IPC分类号： G06F9/46 , G06F13/20 , G06F15/16 , G06F15/173
CPC分类号： G06F9/5044
摘要： A collaboration request may be sent to a host or a peripheral when a job is to be processed. The job may include one or more tasks. The host determines which device is better suited to act as host by analyzing the type of task or job to be executed and the capabilities of the host and peripheral. If the peripheral is better suited to act as host, the host and peripheral swap roles and control of a task or job is transferred to the peripheral. The host and peripheral may return to their default roles once the task or job is complete.
摘要翻译：当要处理作业时，可以向主机或外设发送协作请求。该作业可能包括一个或多个任务。主机通过分析要执行的任务或作业的类型以及主机和外设的功能来确定哪个设备更适合充当主机。如果外设更适合作为主机，主机和外设交换角色以及任务或作业的控制将被传送到外设。任务或作业完成后，主机和外设可能会返回到其默认角色。

8. 发明授权

US07493408B2 USB host protocol 有权
标题翻译： USB主机协议
公开(公告)号：US07493408B2
公开(公告)日：2009-02-17
申请号：US10850327
申请日：2004-05-19
申请人： Yeow Khai Chang , Jerome Tjia , Weng Fei Moo
发明人： Yeow Khai Chang , Jerome Tjia , Weng Fei Moo
IPC分类号： G06F15/16 , G01R31/08 , H04B7/005 , H04L12/54
CPC分类号： G06F13/426
摘要： A method of transferring bulk and control data from a first device to a second device over a USB bus comprises storing transfer descriptors, each including a transfer descriptor header and payload data, in a buffer memory in the first device. The data is read in packets for transfer to the second device, with packets being read from the transfer descriptors cyclically. When the first and second transfer descriptor headers, in first and second transfer descriptors respectively, define a common endpoint, data packets are read from only the first transfer descriptor, until such time as it is detected that all data packets from the first transfer descriptor have been transmitted, and thereafter data packets are read from the second transfer descriptor.
摘要翻译：通过USB总线将批量和控制数据从第一设备传送到第二设备的方法包括将传输描述符（包括传送描述符头和有效载荷数据）存储在第一设备中的缓冲存储器中。数据被读入数据包以传送到第二个设备，数据包循环地从传输描述符读取。当分别在第一和第二传送描述符中的第一和第二传送描述符头部定义公共端点时，仅从第一传送描述符读取数据分组，直到检测到来自第一传送描述符的所有数据分组具有被发送，然后从第二传送描述符读取数据分组。

9. 发明申请

US20070245059A1 Bus Connection Device 有权
标题翻译：总线连接装置
公开(公告)号：US20070245059A1
公开(公告)日：2007-10-18
申请号：US11628129
申请日：2005-05-24
申请人： Jerome Tjia
发明人： Jerome Tjia
IPC分类号： G06F13/40
CPC分类号： G06F13/4027 , G06F2213/0042
摘要： A bus connection device, in the form of a hardware dongle, can be connected to a first electronic device, in the form of a USB peripheral device, and a second electronic device can be connected thereto. The dongle can determine whether the second connected device is a USB host device or a USB peripheral device and, if the second electronic device is a USB host device, it is connected directly to the first electronic device. If the second electronic device is a USB peripheral device, the bus connection device operates to allow the first electronic device to operate as a host device. When the bus connection device is operating to allow the first electronic device to act as a USB host device, it regularly sends tokens to the first electronic device and to the second electronic device, to which the first electronic device can respond by transmitting data intended for the second electronic device, and to which the second electronic device can respond by transmitting data intended for the first electronic device.
摘要翻译：以硬件加密狗形式的总线连接装置可以以USB外围设备的形式连接到第一电子设备，并且可以将第二电子设备连接到第一电子设备。加密狗可以确定第二个连接的设备是USB主机设备还是USB外围设备，如果第二个电子设备是USB主机设备，则它直接连接到第一个电子设备。如果第二电子设备是USB外围设备，则总线连接设备操作以允许第一电子设备作为主机设备操作。当总线连接装置正在操作以允许第一电子设备充当USB主机设备时，它定期向第一电子设备和第二电子设备发送令牌，第一电子设备可以通过发送用于第二电子设备，并且第二电子设备可以通过发送用于第一电子设备的数据来对其进行响应。

10. 发明申请

US20070028011A1 Ubs host controller with dma capability 有权
标题翻译：具有dma功能的Ubs主机控制器
公开(公告)号：US20070028011A1
公开(公告)日：2007-02-01
申请号：US10556453
申请日：2004-05-12
申请人： Chee Lee , Constantin Socol , Jerome Tjia
发明人： Chee Lee , Constantin Socol , Jerome Tjia
IPC分类号： G06F13/28
CPC分类号： G06F13/385
摘要： An embedded host controller, for use in a USB system comprising a processor and an associated system memory, comprises a DMA controller, and the host controller is adapted such that, in order to retrieve data from the associated system memory, a starting address and block length are sent to the DMA controller, and the DMA controller is adapted such that, on receipt of a starting address and block length sent from the host controller, it retrieves the indicated data from the associated system memory. This has the advantage that the embedded host controller can be used with different host microprocessors, without assuming that PCI functionality is available.
摘要翻译：用于包括处理器和相关系统存储器的USB系统中的嵌入式主机控制器包括DMA控制器，并且主机控制器被调整为使得为了从相关联的系统存储器检索数据，起始地址和块长度被发送到DMA控制器，并且DMA控制器被调整为使得在接收到从主机控制器发送的起始地址和块长度时，它从相关联的系统存储器检索指示的数据。这具有的优点是嵌入式主机控制器可以与不同的主机微处理器一起使用，而不需要PCI功能可用。

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