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    • 2. 发明授权
    • Low-power voltage comparator based on quantum tunneling coupled transistors
    • 基于量子隧道耦合晶体管的低功率电压比较器
    • US07495592B1
    • 2009-02-24
    • US11261746
    • 2005-10-27
    • Jeong-Sun MoonKeh-Chung Wang
    • Jeong-Sun MoonKeh-Chung Wang
    • H03M1/00
    • H03M1/368
    • A voltage comparator including a quantum tunneling coupled transistor and a method for tuning the voltage comparator. The comparator includes a quantum tunneling coupled transistor coupled to a resistor and is capable of operating above 10 Giga-samples-per-second or a clock rate of 10 GHz. The comparator has a low power consumption of about 1 mW excluding the power required for clock generation and independent from the sampling rate. The threshold or reference voltage of the comparator is controllable by adjusting the pulse height of the clock signal. The comparator has relatively low hysteresis estimated at about 1 mV.
    • 一种包括量子隧道耦合晶体管的电压比较器和用于调谐电压比较器的方法。 比较器包括耦合到电阻器的量子隧道耦合晶体管,并且能够以超过10千兆采样/秒或10GHz的时钟速率工作。 比较器具有约1mW的低功耗,不包括时钟产生所需的功率,并且独立于采样率。 通过调整时钟信号的脉冲高度可以控制比较器的阈值或参考电压。 比较器估计的滞后相对较低,约为1 mV。
    • 3. 发明授权
    • Non-planar nitride-based heterostructure field effect transistor
    • 非平面氮化物基异质结场效应晶体管
    • US07247893B2
    • 2007-07-24
    • US10932811
    • 2004-09-01
    • Jeong Sun MoonPaul HashimotoWah S. WongDavid E. Grider
    • Jeong Sun MoonPaul HashimotoWah S. WongDavid E. Grider
    • H01L29/20
    • H01L29/66462H01L21/28587H01L21/30612H01L29/2003H01L29/7787
    • A method for fabricating a non-planar heterostructure field effect transistor using group III-nitride materials with consistent repeatable results is disclosed. The method provides a substrate on which at least one layer of semiconductor material is deposited. An AlN layer is deposited on the at least one layer of semiconductor material. A portion of the AlN layer is removed using a solvent to create a non-planar region with consistent and repeatable results. The at least one layer beneath the AlN layer is insoluble in the solvent and therefore acts as an etch stop, preventing any damage to the at least one layer beneath the AlN layer. Furthermore, should the AlN layer incur any surface damage as a result of the reactive ion etching, the damage will be removed when exposed to the solvent to create the non-planar region.
    • 公开了使用具有一致的可重复结果的III族氮化物材料制造非平面异质结构场效应晶体管的方法。 该方法提供其上沉积至少一层半导体材料的衬底。 AlN层沉积在至少一层半导体材料上。 使用溶剂去除一部分AlN层以产生具有一致和可重复结果的非平面区域。 AlN层下面的至少一层不溶于溶剂,因此用作蚀刻停止层,防止对AlN层下面的至少一层的任何损坏。 此外,如果AlN层由于反应离子蚀刻而导致任何表面损伤,则当暴露于溶剂以形成非平面区域时,损伤将被去除。
    • 9. 发明授权
    • Capacitive arrangement for qubit operations
    • 量子位操作的容性安排
    • US07830695B1
    • 2010-11-09
    • US11927402
    • 2007-10-29
    • Jeong-Sun Moon
    • Jeong-Sun Moon
    • G11C13/00G11C11/34G11C11/44H01L31/00
    • G11C11/44G01R33/1284G11C11/5671G11C19/00
    • A capacitive operation method for quantum computing is disclosed where providing a sequence of write pulses above a threshold voltage induces a single charge population, forming a quantum dot (Q-dot). Determining if the single charge population was induced in the Q-dot occurs by monitoring capacitance changes while the writing is performed. Q-bits (Q-dot pairs) are formed without requiring a separate transistor for each Q-dot by multiplexing the calibration. A device which is able to perform the above method is also disclosed. The device utilizes the ability of cryogenic capacitance bridge circuits to measure the capacitance change caused by the introduction of a single charge population to a Q-dot. The device also permits swapping of Q-dot and Q-bit pairs utilizing a signal multiplexed with the voltage pulses that write (e.g. change the charge population) to the Q-dots.
    • 公开了一种用于量子计算的电容性操作方法,其中提供高于阈值电压的写入脉冲序列引起单个电荷群体,形成量子点(Q点)。 通过在执行写入时监测电容变化来确定单个电荷群体是否在Q点中感应。 通过多路复用校准,形成Q位(Q点对),而不需要为每个Q点分离晶体管。 还公开了能够执行上述方法的装置。 该器件利用低电容电桥电路测量由单个电荷群导入Q点导致的电容变化的能力。 该装置还允许利用与将(例如改变电荷群)改变为Q点的电压脉冲多路复用的信号来交换Q点和Q位对。