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1. 发明授权

US08823129B2 Latch-up prevention structure and method for ultra-small high voltage tolerant cell 有权
标题翻译：超小型耐高压电池的锁定防止结构和方法
公开(公告)号：US08823129B2
公开(公告)日：2014-09-02
申请号：US12797782
申请日：2010-06-10
申请人： Da-Wei Lai , Jen-Chou Tseng , Chien-Yuan Lee
发明人： Da-Wei Lai , Jen-Chou Tseng , Chien-Yuan Lee
IPC分类号： H01L27/105 , H01L27/092 , H01L29/06 , H01L27/118
CPC分类号： H01L27/0921 , H01L29/0642 , H01L2027/11892 , H01L2924/0002 , H01L2924/00
摘要： A latch-up prevention structure and method for ultra-small high voltage tolerant cell is provided. In one embodiment, the integrated circuit includes an input and/or output pad, a floating high-voltage n-well (HVNW) connected to the input and/or output pad through a P+ in the floating HVNW and also connected to a first voltage supply, a low-voltage n-well (LVNW) connected to a second voltage supply through a N+ in the LVNW, a HVNW control circuit, and a guard-ring HVNW, where the first voltage supply has higher voltage level than the second voltage supply, guard-ring HVNW is inserted in between the floating HVNW and LVNW to prevent a latch-up path between a P+ in HVNW and N+ in LVNW by using the HVNW control circuit that controls the guard-ring HVNW's voltage level. The guard-ring HVNW's voltage level is matched by the floating HVNW's voltage level.
摘要翻译：提供了一种用于超小型高耐压单元的闭锁预防结构和方法。在一个实施例中，集成电路包括通过浮动HVNW中的P +连接到输入和/或输出焊盘的输入和/或输出焊盘，浮动高压n阱（HVNW），并且还连接到第一电压提供通过LVNW中的N +连接到第二电压源的低电压n阱（LVNW），HVNW控制电路和保护环HVNW，其中第一电压源具有比第二电压更高的电压电平电源，保护环HVNW插入在浮动HVNW和LVNW之间，以防止HVNW中的P +与LVNW中的N +之间的闩锁路径，通过使用控制保护环HVNW的电压电平的HVNW控制电路。保护环HVNW的电压电平与浮动HVNW的电压电平相匹配。

2. 发明授权

US08809905B2 Vertical BJT and SCR for ESD 有权
标题翻译：垂直BJT和SCR用于ESD
公开(公告)号：US08809905B2
公开(公告)日：2014-08-19
申请号：US13339189
申请日：2011-12-28
申请人： Wun-Jie Lin , Ching-Hsiung Lo , Jen-Chou Tseng
发明人： Wun-Jie Lin , Ching-Hsiung Lo , Jen-Chou Tseng
IPC分类号： H01L29/66
CPC分类号： H01L27/0262 , H01L29/732 , H01L29/74
摘要： An electrostatic discharge (ESD) protection device includes a well region formed from semiconductor material with a first doping type and a floating base formed from semiconductor material with a second doping type. The floating base is disposed vertically above the well region. The ESD also includes a first terminal receiving region formed from semiconductor material with a third doping type. The first terminal receiving region is disposed vertically above the floating base. The ESD further includes a second terminal receiving region. The second terminal receiving region is laterally spaced apart from the first terminal receiving region by silicon trench isolation (STI) region. In some embodiments, the second terminal receiving region is formed from semiconductor material with the third doping type to form a bipolar junction transmitter (BJT) or with a fourth doping type to form a silicon controlled rectifier (SCR).
摘要翻译：静电放电（ESD）保护装置包括由具有第一掺杂类型的半导体材料和由具有第二掺杂类型的半导体材料形成的浮动基底形成的阱区。浮动底座垂直设置在井区域上方。 ESD还包括由具有第三掺杂类型的半导体材料形成的第一端子接收区域。第一端子接收区域垂直设置在浮动基座上方。 ESD还包括第二终端接收区域。第二端子接收区域通过硅沟槽隔离（STI）区域与第一端子接收区域横向间隔开。在一些实施例中，第二端子接收区域由具有第三掺杂类型的半导体材料形成以形成双极结发送器（BJT）或具有第四掺杂类型以形成可控硅整流器（SCR）。

3. 发明授权

US08735993B2 FinFET body contact and method of making same 有权
标题翻译： FinFET体接触及其制作方法
公开(公告)号：US08735993B2
公开(公告)日：2014-05-27
申请号：US13363026
申请日：2012-01-31
申请人： Ching-Hsiung Lo , Jam-Wem Lee , Wun-Jie Lin , Jen-Chou Tseng
发明人： Ching-Hsiung Lo , Jam-Wem Lee , Wun-Jie Lin , Jen-Chou Tseng
IPC分类号： H01L27/088
CPC分类号： H01L29/7831 , H01L27/0255 , H01L29/423 , H01L29/66545 , H01L29/66795 , H01L29/78 , H01L29/785
摘要： A semiconductor device may include body contacts on a finFET device for ESD protection. The semiconductor device comprises a semiconductor fin, a source/drain region and a body contact. The source/drain region and the body contact are in the semiconductor fin. A portion of the fin is laterally between the source/drain region and the body contact. The semiconductor fin is on a substrate.
摘要翻译：半导体器件可以包括用于ESD保护的finFET器件上的体接触。半导体器件包括半导体鳍片，源极/漏极区域和主体接触。源极/漏极区域和主体接触处于半导体鳍片中。翅片的一部分横向在源极/漏极区域和身体接触之间。半导体鳍片在衬底上。

4. 发明授权

US08692289B2 Fast turn on silicon controlled rectifiers for ESD protection 有权
标题翻译：快速开启可控硅整流器，实现ESD保护
公开(公告)号：US08692289B2
公开(公告)日：2014-04-08
申请号：US13558154
申请日：2012-07-25
申请人： Yu-Ti Su , Tzu-Heng Chang , Jen-Chou Tseng , Ming-Hsiang Song
发明人： Yu-Ti Su , Tzu-Heng Chang , Jen-Chou Tseng , Ming-Hsiang Song
IPC分类号： H01L29/74 , H01L31/111 , H02H3/00 , H02H7/00 , H02H9/02
CPC分类号： H01L27/0817 , H01L27/0262 , H01L29/7436
摘要： Fast turn on silicon controlled rectifiers for ESD protection. A semiconductor device includes a semiconductor substrate of a first conductivity type; a first well of a second conductivity type; a second well of the second conductivity type; a first diffused region of the first conductivity type and coupled to a first terminal; a first diffused region of the second conductivity type; a second diffused region of the first conductivity type; a second diffused region of the second conductivity type in the second well; wherein the first diffused region of the first conductivity type and the first diffused region of the second conductivity type form a first diode, and the second diffused region of the first conductivity type and the second diffused region of the second conductivity type form a second diode, and the first and second diodes are series coupled between the first terminal and the second terminal.
摘要翻译：快速开启可控硅整流器，实现ESD保护。半导体器件包括第一导电类型的半导体衬底; 第二导电类型的第一阱; 第二导电类型的第二阱; 第一导电类型的第一扩散区域并耦合到第一端子; 第二导电类型的第一扩散区域; 第一导电类型的第二扩散区域; 第二导电类型的第二扩散区域; 其中第一导电类型的第一扩散区域和第二导电类型的第一扩散区域形成第一二极管，并且第一导电类型的第二扩散区域和第二导电类型的第二扩散区域形成第二二极管，并且第一和第二二极管串联耦合在第一端子和第二端子之间。

5. 发明授权

US07329925B2 Device for electrostatic discharge protection 失效
标题翻译：静电放电保护装置
公开(公告)号：US07329925B2
公开(公告)日：2008-02-12
申请号：US11325377
申请日：2006-01-05
申请人： Jen-Chou Tseng
发明人： Jen-Chou Tseng
IPC分类号： H01L23/62 , H01L29/00 , H01L29/72 , H01L29/74 , H01L31/111
CPC分类号： H01L27/0259
摘要： A device for electrostatic discharge (ESD) protection is disclosed. The device for electrostatic discharge protection includes a lateral bipolar transistor and a diode. The semiconductor transistor has an emitter, a base and a collector electrically connected to a first power line (such as Vdd), a second power line (such as Vss) and a bond pad of an integrated circuit respectively. The diode has an n electrode and a p electrode electrically connected to the first power line and the bond pad respectively.
摘要翻译：公开了一种用于静电放电（ESD）保护的装置。用于静电放电保护的装置包括横向双极晶体管和二极管。半导体晶体管具有电连接到第一电力线（例如Vdd）的发射极，基极和集电极，第二电力线（例如V ss）和集成电路的接合焊盘。二极管分别具有与第一电源线和接合焊盘电连接的n电极和p电极。

6. 发明申请

US20140027815A1 Fast Turn On Silicon Controlled Rectifiers for ESD Protection 有权
标题翻译：快速开启用于ESD保护的硅控整流器
公开(公告)号：US20140027815A1
公开(公告)日：2014-01-30
申请号：US13558154
申请日：2012-07-25
申请人： Yu-Ti Su , Tzu-Heng Chang , Jen-Chou Tseng , Ming-Hsiang Song
发明人： Yu-Ti Su , Tzu-Heng Chang , Jen-Chou Tseng , Ming-Hsiang Song
IPC分类号： H01L27/06 , H01L21/8222
CPC分类号： H01L27/0817 , H01L27/0262 , H01L29/7436
摘要： Fast turn on silicon controlled rectifiers for ESD protection. A semiconductor device includes a semiconductor substrate of a first conductivity type; a first well of a second conductivity type; a second well of the second conductivity type; a first diffused region of the first conductivity type and coupled to a first terminal; a first diffused region of the second conductivity type; a second diffused region of the first conductivity type; a second diffused region of the second conductivity type in the second well; wherein the first diffused region of the first conductivity type and the first diffused region of the second conductivity type form a first diode, and the second diffused region of the first conductivity type and the second diffused region of the second conductivity type form a second diode, and the first and second diodes are series coupled between the first terminal and the second terminal.
摘要翻译：快速开启可控硅整流器，实现ESD保护。半导体器件包括第一导电类型的半导体衬底; 第二导电类型的第一阱; 第二导电类型的第二阱; 第一导电类型的第一扩散区域并耦合到第一端子; 第二导电类型的第一扩散区域; 第一导电类型的第二扩散区域; 第二导电类型的第二扩散区域; 其中第一导电类型的第一扩散区域和第二导电类型的第一扩散区域形成第一二极管，并且第一导电类型的第二扩散区域和第二导电类型的第二扩散区域形成第二二极管，并且第一和第二二极管串联耦合在第一端子和第二端子之间。

7. 发明申请

US20080258223A1 ESD PROTECTION DEVICE 审中-公开
标题翻译： ESD保护装置
公开(公告)号：US20080258223A1
公开(公告)日：2008-10-23
申请号：US11775614
申请日：2007-07-10
申请人： Jen-Chou Tseng
发明人： Jen-Chou Tseng
IPC分类号： H01L23/62
CPC分类号： H01L27/0255 , H01L29/8618
摘要： An ESD protection device is provided. The ESD protection device of the present invention includes a semiconductor substrate/well, a first doped region, a second doped region and a third doped region. The first doped region doped with a first dopant is disposed in the semiconductor substrate/well. The second doped region doped with a second dopant is disposed in the semiconductor substrate/well, wherein a predetermined distance is maintained between the second doped region and the first doped region. The third doped region doped with the second dopant is disposed in the first doped region. The ESD protection device of the present invention is adapted for solving the reverse recovery problem of the conventional diode during the bipolar type ESD stressing.
摘要翻译：提供ESD保护装置。本发明的ESD保护器件包括半导体衬底/阱，第一掺杂区，第二掺杂区和第三掺杂区。掺杂有第一掺杂剂的第一掺杂区域设置在半导体衬底/阱中。掺杂有第二掺杂剂的第二掺杂区域设置在半导体衬底/阱中，其中在第二掺杂区域和第一掺杂区域之间保持预定距离。掺杂有第二掺杂剂的第三掺杂区域设置在第一掺杂区域中。本发明的ESD保护器件适用于在双极型ESD应力期间解决传统二极管的反向恢复问题。

8. 发明申请

US20070183104A1 ESD protection device and integrated circuit utilizing the same 审中-公开
标题翻译： ESD保护器件和利用其的集成电路
公开(公告)号：US20070183104A1
公开(公告)日：2007-08-09
申请号：US11453017
申请日：2006-06-15
申请人： Jen-Chou Tseng
发明人： Jen-Chou Tseng
IPC分类号： H02H9/00
CPC分类号： H01L27/0285
摘要： An ESD protection device comprising a first switch, a second switch, a discharge unit, and a detection unit. The first switch is coupled to a first power line. The second switch is coupled between the first switch and a second power line. The discharge unit is coupled between the first and second power lines. The detection unit is coupled between the first and second power lines. The first switch is turned on when an ESD event occurs in the first power line. The second switch is turned on when the ESD event does not occur in the first power line.
摘要翻译：一种ESD保护装置，包括第一开关，第二开关，放电单元和检测单元。第一开关耦合到第一电力线。第二开关耦合在第一开关和第二电源线之间。放电单元耦合在第一和第二电力线之间。检测单元耦合在第一和第二电力线之间。当第一条电源线发生ESD事件时，第一个开关打开。当第一电源线上没有发生ESD事件时，第二个开关导通。

9. 发明申请

US20050224836A1 SILICON CONTROLLED RECTIFIER 失效
标题翻译：硅控整流器
公开(公告)号：US20050224836A1
公开(公告)日：2005-10-13
申请号：US10711542
申请日：2004-09-24
申请人： Jen-Chou Tseng
发明人： Jen-Chou Tseng
IPC分类号： H01L23/60 , H01L27/02 , H01L29/32 , H01L29/68 , H01L29/74
CPC分类号： H01L27/0262 , H01L29/7436
摘要： A silicon controlled rectifier is provided, including: a first conducting-type substrate; two second conducting-type deep wells separately disposed inside the first conducting-type substrate; a gate above the first conducting-type substrate and between the two second conducting-type deep wells; a first source/drain inside one of the two second conducting-type deep wells and at one side of the gate; a second source/drain inside the other of the two second conducting-type deep wells and at the other side of the gate; a first conducting-type doped region inside the first conducting-type substrate; and a first conducting-type doped floating region inside the one of the two second conducting-type deep wells and adjacent to the first source/drain. The first conducting-type doped floating region and the first source/drain constitute an equivalent Zener diode so that the modified silicon controlled rectifier can have a higher holding voltage.
摘要翻译：提供一种可控硅整流器，包括：第一导电型衬底; 分别设置在第一导电型基板内的两个第二导电型深阱; 在第一导电型衬底之上和两个第二导电类型深阱之间的栅极; 在两个第二导电类型深阱之一和栅极一侧的一个内的第一源极/漏极; 两个第二导电类型深阱的另一个内部的第二源极/漏极，以及栅极的另一侧; 第一导电型衬底内的第一导电型掺杂区; 以及在所述两个第二导电类型深阱中的一个内部并且与所述第一源极/漏极相邻的第一导电型掺杂漂浮区域。第一导电型掺杂浮置区和第一源极/漏极构成等效的齐纳二极管，使得改进的可控硅整流器可以具有较高的保持电压。

10. 发明申请

US20130083436A1 ELECTROSTATIC DISCHARGE PROTECTION 有权
标题翻译：静电放电保护
公开(公告)号：US20130083436A1
公开(公告)日：2013-04-04
申请号：US13252396
申请日：2011-10-04
申请人： Jen-Chou TSENG , Tzu-Heng CHANG , Ming-Hsiang SONG
发明人： Jen-Chou TSENG , Tzu-Heng CHANG , Ming-Hsiang SONG
IPC分类号： H02H9/04 , H01L21/768
CPC分类号： H01L27/0292 , H01L21/822 , H01L23/481 , H01L23/60 , H01L27/0255 , H01L27/0262 , H01L27/0266 , H01L27/0285 , H01L2924/0002 , H01L2924/00
摘要： A chip includes a first circuit, a second circuit, a first interconnect, and a least one protection circuit. The first circuit has a first node, a first operational voltage node, and a first reference voltage node. The second circuit has a second node, a second operational voltage node, and a second reference voltage node. The first interconnect is configured to electrically connect the first node and the second node to form a 2.5D or a 3D integrated circuit. The at least one protection circuit is located at one or various locations of the chip.
摘要翻译：芯片包括第一电路，第二电路，第一互连和至少一个保护电路。第一电路具有第一节点，第一工作电压节点和第一参考电压节点。第二电路具有第二节点，第二工作电压节点和第二参考电压节点。第一互连被配置为电连接第一节点和第二节点以形成2.5D或3D集成电路。至少一个保护电路位于芯片的一个或多个位置。

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