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1. 发明授权

US5860111A Coherency for write-back cache in a system designed for write-through cache including export-on-hold 失效
标题翻译：设计用于直写缓存的系统中的回写缓存的一致性，包括导出保持
公开(公告)号：US5860111A
公开(公告)日：1999-01-12
申请号：US496712
申请日：1995-06-29
申请人： Marvin Wayne Martinez, Jr. , Mark Bluhm , Jeffrey S. Byrne , David A. Courtright , Douglas Ewing Duschatko , Raul A. Garibay, Jr. , Margaret R. Herubin
发明人： Marvin Wayne Martinez, Jr. , Mark Bluhm , Jeffrey S. Byrne , David A. Courtright , Douglas Ewing Duschatko , Raul A. Garibay, Jr. , Margaret R. Herubin
IPC分类号： G06F12/08 , G06F12/12
CPC分类号： G06F12/0804 , G06F12/0808 , G06F12/0831 , G06F12/0835
摘要： A write-back coherency system is used, in an exemplary embodiment, to implement write-back caching in an x86 processor installed in a multi-master computer system that does not support a write-back protocol for maintaining coherency between an internal cache and main memory during DMA operations. The write-back coherency system interrupts the normal bus arbitration operation to allow export of dirty data. In response to an arbitration-request (such as HOLD), if the internal cache contains dirty data, the processor is inhibited from providing arbitration-acknowledge (such as HLDA) until the dirty data is exported (the cache is dynamically switched to write-through mode to prevent data in the cache from being made dirty while the bus is arbitrated away). While the requesting bus master is accessing memory, bus snooping is performed and invalidation logic invalidates at least those cache locations corresponding to locations in memory that are affected by the requesting bus master.
摘要翻译：在示例性实施例中，使用回写一致性系统来实现在安装在多主计算机系统中的x86处理器中的回写高速缓存，该多主计算机系统不支持用于维持内部高速缓存与主机之间的一致性的回写协议 DMA操作期间的内存。回写一致性系统中断正常总线仲裁操作，以允许导出脏数据。响应仲裁请求（如HOLD），如果内部缓存包含脏数据，则禁止处理器提供仲裁确认（例如HLDA），直到导出脏数据（高速缓存被动态切换为写入 - 通过模式来防止缓存中的数据在总线被仲裁时被弄脏）。当请求总线主机访问存储器时，执行总线监听，并且无效逻辑至少对应于受请求总线主机影响的存储器中的位置的那些高速缓存位置无效。

2. 发明授权

US5524234A Coherency for write-back cache in a system designed for write-through cache including write-back latency control 失效
标题翻译：设计用于直写缓存的系统中的回写缓存的一致性，包括回写延迟控制
公开(公告)号：US5524234A
公开(公告)日：1996-06-04
申请号：US365972
申请日：1994-12-28
申请人： Marvin W. Martinez, Jr. , Mark Bluhm , Jeffrey S. Byrne , David A. Courtright , Douglas E. Duschatko , Raul A. Garibay, Jr. , Margaret R. Herubin
发明人： Marvin W. Martinez, Jr. , Mark Bluhm , Jeffrey S. Byrne , David A. Courtright , Douglas E. Duschatko , Raul A. Garibay, Jr. , Margaret R. Herubin
IPC分类号： G06F12/08 , G06F12/12 , G06F12/16 , G06F13/16 , G06F13/28
CPC分类号： G06F12/0804 , G06F12/0808 , G06F12/0831 , G06F12/0835
摘要： A write-back coherency system is used, in an exemplary embodiment, to implement write-back caching in an x86 processor installed in a multi-master computer system that does not support a write-back protocol for maintaining coherency between an internal cache and main memory during DMA operations. The write-back coherency system interrupts the normal bus arbitration operation to allow export of dirty data, and includes an X%DIRTY latency-control function. In response to an arbitration-request (such as HOLD), if the internal cache contains dirty data, the processor is inhibited from providing arbitration-acknowledge (such as HLDA) until the dirty data is exported (the cache is dynamically switched to write-through mode to prevent data in the cache from being made dirty while the bus is arbitrated away). While the requesting bus master is accessing memory, bus snooping is performed and invalidation logic invalidates at least those cache locations corresponding to locations in memory that are affected by the requesting bus master. The X%DIRTY function provides write-back latency control by dynamically switching the cache from write-back to write-through mode if a cache write would cause the number of cache locations containing dirty data to exceed a predetermined maximum percentage of the total number of cache locations.
摘要翻译：在示例性实施例中，使用回写一致性系统来实现在安装在多主计算机系统中的x86处理器中的回写高速缓存，该多主计算机系统不支持用于维持内部高速缓存与主机之间的一致性的回写协议 DMA操作期间的内存。回写一致性系统中断正常总线仲裁操作以允许导出脏数据，并且包括X％DIRTY延迟控制功能。响应仲裁请求（如HOLD），如果内部缓存包含脏数据，则禁止处理器提供仲裁确认（例如HLDA），直到导出脏数据（高速缓存被动态切换为写入 - 通过模式来防止缓存中的数据在总线被仲裁时被弄脏）。当请求总线主机访问存储器时，执行总线监听，并且无效逻辑至少对应于受请求总线主机影响的存储器中的位置的那些高速缓存位置无效。如果高速缓存写入将导致包含脏数据的高速缓存位置的数量超过总数的预定最大百分比，则X％DIRTY功能通过动态地将缓存从写回切换到直写模式来提供回写延迟控制缓存位置。

3. 发明授权

US5490156A Cross-coupled parity circuit with charging circuitry to improve response time 失效
标题翻译：交叉耦合奇偶校验电路与充电电路，以提高响应时间
公开(公告)号：US5490156A
公开(公告)日：1996-02-06
申请号：US493018
申请日：1995-06-21
申请人： Jeffrey S. Byrne
发明人： Jeffrey S. Byrne
IPC分类号： G06F11/10 , H03M13/00
CPC分类号： G06F11/10
摘要： A parity circuit generates an output parity bit responsive to a plurality of data input bits. The parity circuit comprises a plurality of transistor stages coupled to the input bits and the output bit, the value of the input bits defining at least one charging path through the transistor stages. The charging path is coupled at first and second nodes to a power supply, such that the charging path is supplied with current at both ends, thereby increasing the responsiveness of the parity circuit.
摘要翻译：奇偶校验电路响应多个数据输入位产生输出奇偶校验位。奇偶校验电路包括耦合到输入位和输出位的多个晶体管级，输入位的值定义至少一个通过晶体管级的充电路径。充电路径在第一和第二节点处耦合到电源，使得充电路径在两端被提供电流，从而增加了奇偶校验电路的响应性。

4. 发明授权

US07538574B1 Transparent field reconfiguration for programmable logic devices 有权
标题翻译：可编程逻辑器件的透明场重新配置
公开(公告)号：US07538574B1
公开(公告)日：2009-05-26
申请号：US11293941
申请日：2005-12-05
申请人： Howard Tang , Jack T. Wong , Clark Wilkinson , Jeffrey S. Byrne
发明人： Howard Tang , Jack T. Wong , Clark Wilkinson , Jeffrey S. Byrne
IPC分类号： H03K19/177
CPC分类号： H03K19/17772 , H03K19/17744 , H03K19/1776
摘要： In accordance with an embodiment of the present invention, a programmable logic device (PLD, such as a field programmable gate array (FPGA)) includes a plurality of input/output blocks having boundary scan cells that are adapted to precondition registers within a logic area of the programmable logic device with desired signal values prior to release of control of the input/output blocks to user-defined logic provided by a reconfiguration.
摘要翻译：根据本发明的实施例，可编程逻辑器件（PLD，诸如现场可编程门阵列（FPGA））包括具有边界扫描单元的多个输入/输出块，所述边界扫描单元适于预处理逻辑区域内的寄存器在将输入/输出块的控制释放到由重新配置提供的用户定义的逻辑之前，具有期望信号值的可编程逻辑器件。

5. 发明授权

US07269771B1 Semiconductor device adapted for forming multiple scan chains 有权
标题翻译：适用于形成多个扫描链的半导体器件
公开(公告)号：US07269771B1
公开(公告)日：2007-09-11
申请号：US10676536
申请日：2003-09-30
申请人： Daniel B. Young , Jeffrey S. Byrne
发明人： Daniel B. Young , Jeffrey S. Byrne
IPC分类号： G01R31/28
CPC分类号： G01R31/318558 , G01R31/318575
摘要： A device includes data input and data output pins such as found in a JTAG port and a first plurality of boundary scan cells. The device is configurable to support a secondary boundary scan cells formed from the first plurality of boundary scan cells and a second plurality of boundary scan cells in at least one external device. In one embodiment, the device includes a demultiplexer which may be configured to support a primary boundary scan chain between the JTAG port and the first plurality of boundary scan cells. The demultiplexer may also be configured to support the secondary boundary scan chain between the JTAG port and the first and the second plurality of boundary scan cells.
摘要翻译：一种设备包括诸如在JTAG端口和第一多个边界扫描单元中找到的数据输入和数据输出引脚。该设备可配置为支持由第一多个边界扫描单元形成的辅助边界扫描单元和至少一个外部设备中的第二多个边界扫描单元。在一个实施例中，该设备包括解复用器，其可被配置为支持JTAG端口和第一多个边界扫描单元之间的主边界扫描链。解复用器还可以被配置为支持JTAG端口与第一和第二多个边界扫描单元之间的次边界扫描链。

6. 发明授权

US5664149A Coherency for write-back cache in a system designed for write-through cache using an export/invalidate protocol 失效
标题翻译：使用导出/无效协议设计用于直写缓存的系统中的回写缓存的一致性
公开(公告)号：US5664149A
公开(公告)日：1997-09-02
申请号：US151489
申请日：1993-11-12
申请人： Marvin Wayne Martinez, Jr. , Mark W. Bluhm , Jeffrey S. Byrne , David A. Courtright , Douglas Ewing Duschatko , Raul A. Garibay, Jr. , Margaret R. Herubin
发明人： Marvin Wayne Martinez, Jr. , Mark W. Bluhm , Jeffrey S. Byrne , David A. Courtright , Douglas Ewing Duschatko , Raul A. Garibay, Jr. , Margaret R. Herubin
IPC分类号： G06F12/08 , G06F12/12 , G06F12/00
CPC分类号： G06F12/0804 , G06F12/0808 , G06F12/0831 , G06F12/0835
摘要： A write-back coherency system, including FLUSH/INVAL and LOCK protocols, is used, in an exemplary embodiment, in a microprocessor used in a computer system that selectively provides to the processor FLUSH and INVAL signals to implement a limited write-back protocol. The FLUSH/INVAL protocol is used by the computer system to control export and invalidate operations. In response to a FLUSH signal, the microprocessor exports dirty data from the cache. If INVAL is also asserted, the cache is also invalidated (i.e., if FLUSH is asserted and INVAL is not asserted, no invalidation is performed). With the LOCK protocol, LOCKed reads are serviced out of the cache for read hits--however, to maintain compatibility with computer systems that expect a LOCK operation to involve a read followed by a write access to external memory, the microprocessor will still run the external LOCKed read cycle, ignoring the returned data.
摘要翻译：在示例性实施例中，在计算机系统中使用的微处理器中使用包括FLUSH / INVAL和LOCK协议的回写一致性系统，其选择性地向处理器提供FLUSH和INVAL信号以实现有限的回写协议。计算机系统使用FLUSH / INVAL协议来控制导出和无效操作。响应于FLUSH信号，微处理器从缓存中导出脏数据。如果INVAL也被置位，则高速缓存也被无效（即，如果FLUSH被断言且INVAL未被置位，则不执行无效）。使用LOCK协议，LOCK读取从高速缓存中进行读取命中，但是为了保持与计算机系统的兼容性，这些计算机系统期望LOCK操作涉及读取，然后对外部存储器进行写访问，微处理器仍然会运行外部锁定的读取周期，忽略返回的数据。

7. 发明授权

US07737723B1 Transparent field reconfiguration for programmable logic devices 有权
标题翻译：可编程逻辑器件的透明场重新配置
公开(公告)号：US07737723B1
公开(公告)日：2010-06-15
申请号：US12467800
申请日：2009-05-18
申请人： Howard Tang , Jack T. Wong , Clark Wilkinson , Jeffrey S. Byrne
发明人： Howard Tang , Jack T. Wong , Clark Wilkinson , Jeffrey S. Byrne
IPC分类号： H03K19/173
CPC分类号： H03K19/17772 , H03K19/17744 , H03K19/1776
摘要： In accordance with an embodiment of the present invention, a programmable logic device (PLD, such as a field programmable gate array (FPGA)) includes a plurality of input/output blocks adapted to precondition registers within the programmable logic device with desired signal values prior to release of control of the input/output blocks to user-defined logic provided by a reconfiguration.
摘要翻译：根据本发明的实施例，可编程逻辑器件（PLD，诸如现场可编程门阵列（FPGA））包括多个输入/输出块，其适于在可编程逻辑器件中预处理寄存器，其具有期望的信号值将输入/输出块的控制释放到由重新配置提供的用户定义的逻辑。

8. 发明授权

US5379240A Shifter/rotator with preconditioned data 失效
标题翻译：具有预处理数据的移位器/转子
公开(公告)号：US5379240A
公开(公告)日：1995-01-03
申请号：US27342
申请日：1993-03-08
申请人： Jeffrey S. Byrne
发明人： Jeffrey S. Byrne
IPC分类号： G06F5/01 , G06F7/38
CPC分类号： G06F5/01
摘要： Rotate circuitry operable to perform rotate operations on various size operands including preconditioning circuitry (10) for duplicating an operand a predetermined number of times to form a preconditioned word. The rotate operation is performed by shifter (22) which shifts the preconditioned word by a specified number of bits. For rotate through carry operations, Cy bit of the carry flag is inserted in the preconditioned word prior to shifting.
摘要翻译：旋转电路可操作以在各种尺寸操作数上执行旋转操作，包括预处理电路（10），用于复制操作数预定次数以形成预处理字。旋转操作由移位器（22）执行，该移位器将预处理字移位指定位数。为了通过进位操作进行旋转，进位标志的Cy位在变速前插入预处理字中。

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