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1. 发明授权

US4856000A Duplicated circuit arrangement for fast transmission and repairability 失效
标题翻译：重复电路布置，可快速传输和修复
公开(公告)号：US4856000A
公开(公告)日：1989-08-08
申请号：US96569
申请日：1987-09-08
申请人： Michel Bauge , Gerard Boudon , Pierre Mollier , Jean-Luc Peter , Yiannis J. Yamour
发明人： Michel Bauge , Gerard Boudon , Pierre Mollier , Jean-Luc Peter , Yiannis J. Yamour
IPC分类号： G06F11/18 , G06F11/16
CPC分类号： G06F11/16
摘要： Duplicated circuit arrangement comprising a main processor (30) and its P bit data bus (44), and two identical redundant devices (21:22), each device is comprised of a processing element (23;35) performing the same task in parallel on a P bits word, and send/receive circuits (24,25;36,37) controlled by the main processor through lines (SR11 to SR22) to transmit said word to and from said main processor. For each device, the send/receive circuits are split into two parts. Send/receive circuit of the first device (21) is split in two parts (24, 25); the first part (24) handles the P/2 Most Significant Bits (MSB's) and the second part (25) handles the P/2 Less Significant Bits (LSB's). In normal operation, during the transmission step, only the first part (24) is allowed to send bits on one half (33) of the data bus (44). Symmetrically send/receive circuit of the second device (22), is also split in two parts (36, 37); the first section (36) handles the P/2 Most Significant bits (MSB's) and the second part (37) handles the P/2 Less Significant Bits Z(LSB's); only the second part (37) is allowed to send bits on the other half (34) of the data bus (44). Therefore, the data bus driving effort is equally shared between the two devices, the maximum number of simultaneous switching is P/2 for each device. This reduction allows greater transmission speed on large busses.

2. 发明授权

US5511078A Method and apparatus for correction errors in a memory 失效
标题翻译：存储器校正误差的方法和装置
公开(公告)号：US5511078A
公开(公告)日：1996-04-23
申请号：US154686
申请日：1993-11-18
申请人： Gerard Barucchi , Philippe Cuny , Philippe Klein , Olivier Maurel , Jean-Luc Peter
发明人： Gerard Barucchi , Philippe Cuny , Philippe Klein , Olivier Maurel , Jean-Luc Peter
IPC分类号： G06F11/10 , H03M13/15
CPC分类号： G06F11/106 , H03M13/151 , G06F11/1028
摘要： The method and apparatus for correcting one B-bit block in error in a memory organized in words comprising N B-bit blocks consist of appending to the data bits to be written into the memory words a limited number of error correction bits computed from a depopulated parity check matrix which gives the capability of only correcting one block in error and improving the memory failure rate by cyclically reading each word, correcting a block found in error if any and writing the corrected data bits with the corresponding error correction bits in place of the read word.
摘要翻译：用于校正由包括N个B位块的单词组织的存储器中的一个B位块的错误校正方法和装置包括附加到要写入存储器字的数据位，从有限的数量的错误校正位奇偶校验矩阵，其给出仅校正错误的一个块的能力，并且通过循环读取每个字来改善存储器故障率，校正错误中发现的块，如果有的话，用相应的纠错位写入校正的数据位，代替读字

3. 发明授权

US4295210A Power supply system for monolithic cells 失效
标题翻译：整体式电池供电系统
公开(公告)号：US4295210A
公开(公告)日：1981-10-13
申请号：US71826
申请日：1979-09-04
申请人： Herve Beranger , Claude Marzin , Dominique M. Omet , Jean-Luc Peter
发明人： Herve Beranger , Claude Marzin , Dominique M. Omet , Jean-Luc Peter
IPC分类号： H02J1/00 , G05F3/22 , G06F1/26 , G06F12/16 , G11C11/41 , G11C11/411 , G11C11/413 , G11C11/415 , G11C11/40
CPC分类号： G11C11/415 , G05F3/22 , G11C11/4116
摘要： A power-supply system for use in a monolithic memory characterized in that the power dissipation of the memory is reduced. Each word line is connected to a current switch circuit comprised of a first transistor the collector of which is connected to a voltage V1, its base being connected to the output of the address decoder, a second transistor the collector of which is connected to a voltage V2. V3 being the second voltage impressed on the memory cells (where .vertline.V2.vertline. is larger in magnitude than .vertline.V1.vertline. and .vertline.V3.vertline. is larger in magnitude than .vertline.V2.vertline.). The emitters are connected to each other and to the corresponding word line. According to the state of the decoder output, the first or the second transistor is conducting, whereby the selected cells are subjected to a voltage having a magnitude of .vertline.V3-V1.vertline. and the non-selected cells are subjected to a voltage having a magnitude of .vertline.V3-V2.vertline..
摘要翻译：一种用于单片存储器的电源系统，其特征在于减少了存储器的功耗。每个字线连接到由第一晶体管组成的电流开关电路，该第一晶体管的集电极连接到电压V1，其基极连接到地址解码器的输出，第二晶体管的集电极连接到电压 V2。 V3是施加在存储器单元上的第二电压（其中| V 2 |的量值大于| V 1 |和| V 3 |的量值大于| V 2 |）。发射器彼此连接并连接到相应的字线。根据解码器输出的状态，第一或第二晶体管导通，由此所选择的单元受到具有| V3-V1 |的大小的电压，并且未选择的单元经受具有幅度的电压的| V3-V2|。

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