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1. 发明授权

US4725566A Method of forming at least two metallizations of a semiconductor component, covered with a dielectric layer 失效
标题翻译：形成覆盖有介电层的半导体部件的至少两个金属化的方法
公开(公告)号：US4725566A
公开(公告)日：1988-02-16
申请号：US871869
申请日：1986-06-09
申请人： Tung Pham Ngu , Jean Chevrier
发明人： Tung Pham Ngu , Jean Chevrier
IPC分类号： H01L21/285 , H01L21/338 , H01L21/768 , B05D5/12
CPC分类号： H01L29/66863 , H01L21/28587 , H01L21/7688 , Y10S438/947 , Y10S438/951 , Y10S438/98
摘要： A method is provided for forming metallizations on a semiconductor component, which are closer together than is possible with the present day masking technology.In accordance with the invention, a pattern of minimum dimensions is defined in a mask by means of two openings. This pattern is underetched, either by light over-exposure, or by particle back-scattering. Two metallizations are deposited, directionally in the bottom of the openings then a dielectric layer is deposited, non directionally, on the metallizations, the mask is removed by dissolution.
摘要翻译：提供了一种用于在半导体部件上形成金属化的方法，该方法比当今的掩模技术更可靠。根据本发明，通过两个开口在掩模中限定最小尺寸的图案。这种模式是通过光过度曝光或通过粒子反向散射未消除的。两个金属化方向地沉积在开口的底部，然后电介质层在非金属化层上非定向地沉积，通过溶解除去掩模。

2. 发明授权

US4742026A Method for the selective dry etching of layers of III-V group semiconductive materials 失效
标题翻译： III-V族半导体材料层选择性干蚀刻方法
公开(公告)号：US4742026A
公开(公告)日：1988-05-03
申请号：US42819
申请日：1987-04-27
申请人： Jean Vatus , Jean Chevrier
发明人： Jean Vatus , Jean Chevrier
IPC分类号： H01L21/306 , H01L29/47 , H01L21/465
CPC分类号： H01L21/30621 , H01L29/475 , Y10S148/131
摘要： The invention pertains to a method for the selective etching of a surface layer which is automatically stopped at a subjacent layer.According to the invention, a first layer of a material containing gallium is selectively etched with respect to a second layer containing aluminium by reactive ion etching in the presence of a pure freon plasma C Cl.sub.2 F.sub.2. At low pressures (0.5 to 2.5 pascals), the etching is anisotropic and makes it possible to etch the gate recess of a field effect transistor. At a higher pressure (6 to 10 pascals), the etching is isotropic and makes it possible to sub-etch the first layer.Application to the manufacture of field effect transistors made of group III-V materials, with low access resistances.
摘要翻译：本发明涉及一种用于选择性蚀刻表面层的方法，该表面层在下层自动停止。根据本发明，在纯氟利昂等离子体CCl 2 F 2的存在下，通过反应离子蚀刻，相对于含有铝的第二层选择性地蚀刻包含镓的材料的第一层。在低压（0.5至2.5帕斯卡）时，蚀刻是各向异性的，并且可以蚀刻场效应晶体管的栅极凹槽。在更高的压力（6至10帕斯卡），蚀刻是各向同性的，并且可以对第一层进行次蚀刻。应用于制造由III-V族材料制成的场效应晶体管，具有低访问阻抗。

3. 发明授权

US4539501A Epitaxial structure with increased piezoelectric effect and a surface acoustic wave electronic device comprising such a structure 失效
标题翻译：具有增加的压电效应的外延结构和包括这种结构的表面声波电子器件
公开(公告)号：US4539501A
公开(公告)日：1985-09-03
申请号：US563251
申请日：1983-12-19
申请人： Linh N. Trong , Jean Chevrier
发明人： Linh N. Trong , Jean Chevrier
IPC分类号： H01L21/20 , H01L27/20 , H01L41/00 , H01L41/18 , H03H9/02 , H03H9/05 , H01L41/08
CPC分类号： H03H9/0542 , H01L27/20 , H01L41/187 , H03H9/02574
摘要： An epitaxial structure in which a constraint imposed by forced epitaxy causes an increase in the piezoelectric effect of a group of layers. The structure which provides this effect utilizes a semi-insulating substrate made from a first material on which is deposited by forced epitaxy a layer of a second material, the two materials are in crystalline mesh parameter disharmony, which creates in said layer a constraint increasing its piezoelectricity. On the constrained layer are deposited two groups of alternated "deforming" and "deformed" layers of the two materials. The thickness of the structure is sufficient to allow propagation of the surface waves. The advantage of this structure is that it allows two transducers such as transistors to be integrated on or at the side of this structure.
摘要翻译：其中由强制外延施加的约束导致一组层的压电效应增加的外延结构。提供这种效果的结构利用由第一材料制成的半绝缘衬底，其上通过强制外延沉积第二材料层，两种材料处于结晶网格参数不协调，其在所述层中产生约束，从而增加其压电。在约束层上沉积两组交替的“变形”和“变形”两种材料。结构的厚度足以允许表面波的传播。这种结构的优点在于它允许两个换能器如晶体管集成在该结构的一侧或侧面。

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