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1. 发明申请

US20130020708A1 Copper Interconnects Separated by Air Gaps and Method of Making Thereof 有权
标题翻译：铜互连由空气间隙分开及其制作方法
公开(公告)号：US20130020708A1
公开(公告)日：2013-01-24
申请号：US13186094
申请日：2011-07-19
申请人： Vinod R. Purayath , James K. Kai , Jayavel Pachamuthu , Jarrett Jun Liang , George Matamis
发明人： Vinod R. Purayath , James K. Kai , Jayavel Pachamuthu , Jarrett Jun Liang , George Matamis
IPC分类号： H01L23/48 , H01L21/283
CPC分类号： H01L23/53238 , H01L21/7682 , H01L21/76834 , H01L21/76849 , H01L21/76882 , H01L21/76885 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device including a plurality of copper interconnects. At least a first portion of the plurality of copper interconnects has a meniscus in a top surface. The semiconductor device also includes a plurality of air gaps, wherein each air gap of the plurality of air gaps is located between an adjacent pair of at least the first portion of the plurality of bit lines.
摘要翻译：一种包括多个铜互连的半导体器件。多个铜互连的至少第一部分在顶面具有弯液面。半导体器件还包括多个气隙，其中多个气隙中的每个气隙位于多个位线的至少第一部分的相邻对之间。

2. 发明申请

US20120178235A1 Air Isolation In High Density Non-Volatile Memory 有权
标题翻译：高密度非易失性存储器中的空气隔离
公开(公告)号：US20120178235A1
公开(公告)日：2012-07-12
申请号：US13348619
申请日：2012-01-11
申请人： Jayavel Pachamuthu , Vinod R. Purayath , George Matamis
发明人： Jayavel Pachamuthu , Vinod R. Purayath , George Matamis
IPC分类号： H01L21/764
CPC分类号： H01L27/11521 , H01L21/764 , H01L27/11568
摘要： Air gap isolation in non-volatile memory arrays and related fabrication processes are provided. Air gaps are formed at least partially in isolation regions between active areas of the substrate. The air gaps may further extend above the substrate surface between adjacent layer stack columns. A sacrificial material is formed at least partially in the isolation regions, followed by forming a dielectric liner. The sacrificial material is removed to define air gaps prior to forming the control gate layer and then etching it and the layer stack columns to form individual control gates and columns of non-volatile storage elements.
摘要翻译：提供了非易失性存储器阵列中的气隙隔离和相关制造工艺。至少部分地在衬底的有源区域之间的隔离区域中形成气隙。气隙可以在相邻层堆叠柱之间的衬底表面之上进一步延伸。至少部分地在隔离区域中形成牺牲材料，随后形成电介质衬垫。去除牺牲材料以在形成控制栅极层之前限定气隙，然后蚀刻它和层堆叠列以形成单独的控制栅极和非易失性存储元件的列。

3. 发明授权

US09460931B2 High aspect ratio memory hole channel contact formation 有权
标题翻译：高纵横比记忆孔通道接触形成
公开(公告)号：US09460931B2
公开(公告)日：2016-10-04
申请号：US14225176
申请日：2014-03-25
申请人： Jayavel Pachamuthu , Johann Alsmeier , Raghuveer S. Makala , Yao-Sheng Lee
发明人： Jayavel Pachamuthu , Johann Alsmeier , Raghuveer S. Makala , Yao-Sheng Lee
IPC分类号： H01L21/28 , H01L21/8246 , H01L27/115 , H01L29/792 , H01L29/66 , H01L29/788
CPC分类号： H01L21/28282 , H01L21/28273 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11582 , H01L29/66825 , H01L29/66833 , H01L29/7889 , H01L29/7926
摘要： A memory device and a method of fabricating a memory device that includes forming a protrusion over a substrate, an etch stop layer over the protrusion, and a stack of alternating material layers over the etch stop layer. The method further includes etching the stack to the etch stop layer to form a memory opening having a first width dimension proximate to the etch stop layer, etching the etch stop layer to provide a void area between the protrusion and a bottom of the memory opening, where the void area has a second width dimension that is larger than the first width dimension, forming a memory film over a sidewall of the memory opening and within the void area over the top surface of the protrusion, etching the memory film to expose the protrusion, and forming a semiconductor channel in the memory opening that is electrically coupled to the protrusion.
摘要翻译：一种存储器件和一种制造存储器件的方法，所述存储器件包括在衬底上形成突起，在所述突起上方形成蚀刻停止层，以及在所述蚀刻停止层上方的交替材料层堆叠。所述方法还包括将所述叠层蚀刻到所述蚀刻停止层以形成具有靠近所述蚀刻停止层的第一宽度尺寸的存储器开口，蚀刻所述蚀刻停止层以在所述突起与所述存储器开口的底部之间提供空隙区域，其中所述空隙区域具有大于所述第一宽度尺寸的第二宽度尺寸，在所述存储器开口的侧壁上并且在所述突起的顶表面上方的所述空隙区域内形成记忆膜，蚀刻所述存储膜以暴露所述突起并且在与所述突起电耦合的所述存储器开口中形成半导体通道。

4. 发明授权

US08575000B2 Copper interconnects separated by air gaps and method of making thereof 有权
标题翻译：由空气间隙分离的铜互连及其制造方法
公开(公告)号：US08575000B2
公开(公告)日：2013-11-05
申请号：US13186094
申请日：2011-07-19
申请人： Vinod R. Purayath , James K. Kai , Jayavel Pachamuthu , Jarrett Jun Liang , George Matamis
发明人： Vinod R. Purayath , James K. Kai , Jayavel Pachamuthu , Jarrett Jun Liang , George Matamis
IPC分类号： H01L21/76
CPC分类号： H01L23/53238 , H01L21/7682 , H01L21/76834 , H01L21/76849 , H01L21/76882 , H01L21/76885 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device including a plurality of copper interconnects. At least a first portion of the plurality of copper interconnects has a meniscus in a top surface. The semiconductor device also includes a plurality of air gaps, wherein each air gap of the plurality of air gaps is located between an adjacent pair of at least the first portion of the plurality of bit lines.
摘要翻译：一种包括多个铜互连的半导体器件。多个铜互连的至少第一部分在顶面具有弯液面。半导体器件还包括多个气隙，其中多个气隙中的每个气隙位于多个位线的至少第一部分的相邻对之间。

5. 发明申请

US20150076584A1 HIGH ASPECT RATIO MEMORY HOLE CHANNEL CONTACT FORMATION 有权
标题翻译：高比例记忆孔通道接触形成
公开(公告)号：US20150076584A1
公开(公告)日：2015-03-19
申请号：US14225176
申请日：2014-03-25
申请人： Jayavel Pachamuthu , Johann Alsmeier , Raghuveer S. Makala , Yao-Sheng Lee
发明人： Jayavel Pachamuthu , Johann Alsmeier , Raghuveer S. Makala , Yao-Sheng Lee
IPC分类号： H01L29/788 , H01L29/792 , H01L21/28
CPC分类号： H01L21/28282 , H01L21/28273 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11582 , H01L29/66825 , H01L29/66833 , H01L29/7889 , H01L29/7926
摘要： A memory device and a method of fabricating a memory device that includes forming a protrusion over a substrate, an etch stop layer over the protrusion, and a stack of alternating material layers over the etch stop layer. The method further includes etching the stack to the etch stop layer to form a memory opening having a first width dimension proximate to the etch stop layer, etching the etch stop layer to provide a void area between the protrusion and a bottom of the memory opening, where the void area has a second width dimension that is larger than the first width dimension, forming a memory film over a sidewall of the memory opening and within the void area over the top surface of the protrusion, etching the memory film to expose the protrusion, and forming a semiconductor channel in the memory opening that is electrically coupled to the protrusion.
摘要翻译：一种存储器件和一种制造存储器件的方法，所述存储器件包括在衬底上形成突起，在所述突起上方形成蚀刻停止层，以及在所述蚀刻停止层上方的交替材料层堆叠。所述方法还包括将所述叠层蚀刻到所述蚀刻停止层以形成具有靠近所述蚀刻停止层的第一宽度尺寸的存储器开口，蚀刻所述蚀刻停止层以在所述突起与所述存储器开口的底部之间提供空隙区域，其中所述空隙区域具有大于所述第一宽度尺寸的第二宽度尺寸，在所述存储器开口的侧壁上并且在所述突起的顶表面上方的所述空隙区域内形成记忆膜，蚀刻所述存储膜以暴露所述突起并且在与所述突起电耦合的所述存储器开口中形成半导体通道。

6. 发明授权

US08530297B2 Process for fabricating non-volatile storage 有权
标题翻译：制造非易失性储存的方法
公开(公告)号：US08530297B2
公开(公告)日：2013-09-10
申请号：US12762341
申请日：2010-04-18
申请人： Jayavel Pachamuthu , Vinod R. Purayath
发明人： Jayavel Pachamuthu , Vinod R. Purayath
IPC分类号： H01L21/8238 , G11C16/04
CPC分类号： H01L27/11521 , H01L21/28273
摘要： Fabricating non-volatile storage includes creating gate stacks with hard masks on top of the gate stacks. The gate stacks include two polysilicon layers and a dielectric layer between the two polysilicon layers. A portion of the hard mask over each gate stack is removed, leaving two separate tapered sections of each of the hard masks positioned above an upper polysilicon layer of the gate stacks. After the removing the portion of the hard masks, fluorine is implanted into the upper polysilicon layer of the gate stacks. Metal is added on the top surface of the upper polysilicon layer of the floating gate stacks. A silicidation process for the metal and the upper polysilicon layer of the gate stacks is preformed and the remaining tapered sections of the hard mask are removed. Other control lines can then be added.
摘要翻译：制造非易失性存储器包括在栅极堆叠顶部创建具有硬掩模的栅极堆叠。栅堆叠包括两个多晶硅层和两个多晶硅层之间的介电层。去除每个栅极堆叠上的硬掩模的一部分，留下每个硬掩模的两个分开的锥形部分位于栅极堆叠的上部多晶硅层上方。在去除硬掩模的部分之后，将氟注入到栅堆叠的上多晶硅层中。在浮栅堆叠的上多晶硅层的顶表面上添加金属。对栅极叠层的金属和上部多晶硅层进行硅化处理，并除去硬掩模的剩余的锥形部分。然后可以添加其他控制线。

7. 发明授权

US08778749B2 Air isolation in high density non-volatile memory 有权
标题翻译：高密度非易失性存储器中的空气隔离
公开(公告)号：US08778749B2
公开(公告)日：2014-07-15
申请号：US13348619
申请日：2012-01-11
申请人： Jayavel Pachamuthu , Vinod R. Purayath , George Matamis
发明人： Jayavel Pachamuthu , Vinod R. Purayath , George Matamis
IPC分类号： H01L21/764
CPC分类号： H01L27/11521 , H01L21/764 , H01L27/11568
摘要： Air gap isolation in non-volatile memory arrays and related fabrication processes are provided. Air gaps are formed at least partially in isolation regions between active areas of the substrate. The air gaps may further extend above the substrate surface between adjacent layer stack columns. A sacrificial material is formed at least partially in the isolation regions, followed by forming a dielectric liner. The sacrificial material is removed to define air gaps prior to forming the control gate layer and then etching it and the layer stack columns to form individual control gates and columns of non-volatile storage elements.
摘要翻译：提供了非易失性存储器阵列中的气隙隔离和相关制造工艺。至少部分地在衬底的有源区域之间的隔离区域中形成气隙。气隙可以在相邻层堆叠柱之间的衬底表面之上进一步延伸。至少部分地在隔离区域中形成牺牲材料，随后形成电介质衬垫。去除牺牲材料以在形成控制栅极层之前限定气隙，然后蚀刻它和层堆叠列以形成单独的控制栅极和非易失性存储元件的列。

8. 发明申请

US20110256707A1 PROCESS FOR FABRICATING NON-VOLATILE STORAGE 有权
标题翻译：制造非挥发性储存的方法
公开(公告)号：US20110256707A1
公开(公告)日：2011-10-20
申请号：US12762341
申请日：2010-04-18
申请人： Jayavel Pachamuthu , Vinod R. Purayath
发明人： Jayavel Pachamuthu , Vinod R. Purayath
IPC分类号： H01L21/28
CPC分类号： H01L27/11521 , H01L21/28273
摘要： Fabricating non-volatile storage includes creating gate stacks with hard masks on top of the gate stacks. The gate stacks include two polysilicon layers and a dielectric layer between the two polysilicon layers. A portion of the hard mask over each gate stack is removed, leaving two separate tapered sections of each of the hard masks positioned above an upper polysilicon layer of the gate stacks. After the removing the portion of the hard masks, fluorine is implanted into the upper polysilicon layer of the gate stacks. Metal is added on the top surface of the upper polysilicon layer of the floating gate stacks. A silicidation process for the metal and the upper polysilicon layer of the gate stacks is preformed and the remaining tapered sections of the hard mask are removed. Other control lines can then be added.
摘要翻译：制造非易失性存储器包括在栅极堆叠顶部创建具有硬掩模的栅极堆叠。栅堆叠包括两个多晶硅层和两个多晶硅层之间的介电层。去除每个栅极堆叠上的硬掩模的一部分，留下每个硬掩模的两个分开的锥形部分位于栅极堆叠的上部多晶硅层上方。在去除硬掩模的部分之后，将氟注入到栅堆叠的上多晶硅层中。在浮栅堆叠的上多晶硅层的顶表面上添加金属。对栅极叠层的金属和上部多晶硅层进行硅化处理，并除去硬掩模的剩余的锥形部分。然后可以添加其他控制线。

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