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1. 发明申请

US20130238918A1 Connected Standby Sleep State 有权
标题翻译：连接待机休眠状态
公开(公告)号：US20130238918A1
公开(公告)日：2013-09-12
申请号：US13888614
申请日：2013-05-07
申请人： Jawad Haj-Yihia
发明人： Jawad Haj-Yihia
IPC分类号： G06F1/32
CPC分类号： G06F1/3234 , G06F1/3243 , Y02D10/152
摘要： Power consumption and dissipation during sleep states of processors is reduced using a novel connected standby sleep state. In the connected standby sleep state a dedicated power plane is used to maintain processor context. To conserve power, unnecessary components on the processor are powered down, including all of the clock components, and wakeup sources previously directed to the processor are directed to a platform control hub. The platform control hub sustains certain architectural functions for the processor during connected standby sleep state, and manages the wakeup logic for returning the processor to the preceding sleep state.
摘要翻译：使用新颖的连接待机睡眠状态降低处理器睡眠状态期间的功耗和耗散。在连接的待机休眠状态下，使用专用电源平面来维护处理器环境。为了节省电力，处理器上的不必要的组件被关闭，包括所有时钟组件，以及先前指向处理器的唤醒源被引导到平台控制中心。平台控制集线器在连接的待机睡眠状态期间维持处理器的某些架构功能，并且管理用于将处理器返回到先前睡眠状态的唤醒逻辑。

2. 发明申请

US20120102346A1 CONNECTED STANDBY SLEEP STATE 有权
标题翻译：连接待机休眠状态
公开(公告)号：US20120102346A1
公开(公告)日：2012-04-26
申请号：US13341731
申请日：2011-12-30
申请人： Jawad Haj-Yihia
发明人： Jawad Haj-Yihia
IPC分类号： G06F1/32
CPC分类号： G06F1/3234 , G06F1/3243 , Y02D10/152
摘要： Power consumption and dissipation during sleep states of processors is reduced using a novel connected standby sleep state. In the connected standby sleep state a dedicated power plane is used to maintain processor context. To conserve power, unnecessary components on the processor are powered down, including all of the clock components, and wakeup sources previously directed to the processor are directed to a platform control hub. The platform control hub sustains certain architectural functions for the processor during connected standby sleep state, and manages the wakeup logic for returning the processor to the preceding sleep state.
摘要翻译：使用新颖的连接待机睡眠状态降低处理器睡眠状态期间的功耗和耗散。在连接的待机休眠状态下，使用专用电源平面来维护处理器环境。为了节省电力，处理器上的不必要的组件被关闭，包括所有时钟组件，以及先前指向处理器的唤醒源被引导到平台控制中心。平台控制集线器在连接的待机睡眠状态期间维持处理器的某些架构功能，并且管理用于将处理器返回到先前睡眠状态的唤醒逻辑。

3. 发明申请

US20120102342A1 ACTIVE DISPLAY PROCESSOR SLEEP STATE 有权
标题翻译：主动显示处理器休眠状态
公开(公告)号：US20120102342A1
公开(公告)日：2012-04-26
申请号：US13341767
申请日：2011-12-30
申请人： Jawad Haj-Yihia
发明人： Jawad Haj-Yihia
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3265 , G06F1/3287 , G06F3/14 , G09G5/391 , G09G2330/021 , Y02D10/153 , Y02D10/171
摘要： Power consumption and dissipation is reduced during active display of content from an internal display buffer using a power supply topology that powers a display subsystem separately from the other components of a CPU. The power supply topology enables a processor to enter a sleep state without disabling the active display of content. The processor enters a processor sleep state when the display buffer is full and the processor components are no longer needed. The processor exits the processor sleep state when the display buffer is empty and operates in conjunction with the display subsystem to fill the buffer with more content. The processor continues to enter and exit the processor sleep states as appropriate until active display ends.
摘要翻译：使用将显示子系统与CPU的其他组件分开供电的电源拓扑，从内部显示缓冲器主动显示内容时，功耗和功耗降低。电源拓扑使处理器进入睡眠状态，而不会禁用内容的主动显示。当显示缓冲区已满并且处理器组件不再需要时，处理器进入处理器休眠状态。当显示缓冲区为空时，处理器退出处理器休眠状态，并与显示子系统一起运行，以更多的内容填充缓冲区。处理器继续适当地进入和退出处理器休眠状态，直到有效显示结束。

4. 发明授权

US09323307B2 Active display processor sleep state 有权
标题翻译：主动显示处理器休眠状态
公开(公告)号：US09323307B2
公开(公告)日：2016-04-26
申请号：US13341767
申请日：2011-12-30
申请人： Jawad Haj-Yihia
发明人： Jawad Haj-Yihia
IPC分类号： G06F1/32 , G06F3/14 , G09G5/391
CPC分类号： G06F1/3203 , G06F1/3265 , G06F1/3287 , G06F3/14 , G09G5/391 , G09G2330/021 , Y02D10/153 , Y02D10/171
摘要： Power consumption and dissipation is reduced during active display of content from an internal display buffer using a power supply topology that powers a display subsystem separately from the other components of a CPU. The power supply topology enables a processor to enter a sleep state without disabling the active display of content. The processor enters a processor sleep state when the display buffer is full and the processor components are no longer needed. The processor exits the processor sleep state when the display buffer is empty and operates in conjunction with the display subsystem to fill the buffer with more content. The processor continues to enter and exit the processor sleep states as appropriate until active display ends.
摘要翻译：使用将显示子系统与CPU的其他组件分开供电的电源拓扑，从内部显示缓冲器主动显示内容时，功耗和功耗降低。电源拓扑使处理器进入睡眠状态，而不会禁用内容的主动显示。当显示缓冲区已满并且处理器组件不再需要时，处理器进入处理器休眠状态。当显示缓冲区为空时，处理器退出处理器休眠状态，并与显示子系统一起运行，以更多的内容填充缓冲区。处理器继续适当地进入和退出处理器休眠状态，直到有效显示结束。

5. 发明申请

US20140006833A1 MAXIMUM CURRENT THROTTLING 有权
标题翻译：最大电流曲线
公开(公告)号：US20140006833A1
公开(公告)日：2014-01-02
申请号：US13537319
申请日：2012-06-29
申请人： Ruoying Mary Ma , Craig Forbell , Soethiha Soe , Jawad Haj-Yihia
发明人： Ruoying Mary Ma , Craig Forbell , Soethiha Soe , Jawad Haj-Yihia
IPC分类号： G06F1/26
CPC分类号： G06F1/28 , G06F1/26 , G06F1/30 , G06F1/3203
摘要： Systems and methods may provide for monitoring a current provided from a voltage regulator to a non-core region of a processor, and asserting a throttle signal to the non-core region of the processor if the current exceeds a supply capability threshold of the voltage regulator. In one example, a specified current supply capability of the non-core region is greater than a current supply capability of the voltage regulator, and the supply capability threshold is less than the specified current supply capability of the non-core region and an over current protection threshold of the non-core region.
摘要翻译：系统和方法可以提供监视从电压调节器提供给处理器的非核心区域的电流，以及如果电流超过电压调节器的供应能力阈值，则将该节气门信号断言到处理器的非核心区域。在一个示例中，非核心区域的指定电流供应能力大于电压调节器的电流供应能力，并且供电能力阈值小于非核心区域的指定电流供应能力和过电流非核心区域的保护阈值。

6. 发明申请

US20130191667A1 CONNECTED STANDBY SLEEP STATE 有权
标题翻译：连接待机休眠状态
公开(公告)号：US20130191667A1
公开(公告)日：2013-07-25
申请号：US13795145
申请日：2013-03-12
申请人： JAWAD HAJ-YIHIA
发明人： JAWAD HAJ-YIHIA
IPC分类号： G06F1/32
CPC分类号： G06F1/3234 , G06F1/3243 , Y02D10/152
摘要： Power consumption and dissipation during sleep states of processors is reduced using a novel connected standby sleep state. In the connected standby sleep state a dedicated power plane is used to maintain processor context. To conserve power, unnecessary components on the processor are powered down, including all of the clock components, and wakeup sources previously directed to the processor are directed to a platform control hub. The platform control hub sustains certain architectural functions for the processor during connected standby sleep state, and manages the wakeup logic for returning the processor to the preceding sleep state.
摘要翻译：使用新颖的连接待机睡眠状态降低处理器睡眠状态期间的功耗和耗散。在连接的待机休眠状态下，使用专用电源平面来维护处理器环境。为了节省电力，处理器上的不必要的组件被关闭，包括所有时钟组件，以及先前指向处理器的唤醒源被引导到平台控制中心。平台控制集线器在连接的待机睡眠状态期间维持处理器的某些架构功能，并且管理用于将处理器返回到先前睡眠状态的唤醒逻辑。

7. 发明授权

US08230247B2 Transferring architectural functions of a processor to a platform control hub responsive to the processor entering a deep sleep state 有权
标题翻译：响应于处理器进入深度睡眠状态，将处理器的架构功能转移到平台控制中心
公开(公告)号：US08230247B2
公开(公告)日：2012-07-24
申请号：US13341731
申请日：2011-12-30
申请人： Jawad Haj-Yihia
发明人： Jawad Haj-Yihia
IPC分类号： G06F1/26 , G06F1/32 , G06F1/18
CPC分类号： G06F1/3234 , G06F1/3243 , Y02D10/152
摘要： Power consumption and dissipation during sleep states of processors is reduced using a novel connected standby sleep state. In the connected standby sleep state a dedicated power plane is used to maintain processor context. To conserve power, unnecessary components on the processor are powered down, including all of the clock components, and wakeup sources previously directed to the processor are directed to a platform control hub. The platform control hub sustains certain architectural functions for the processor during connected standby sleep state, and manages the wakeup logic for returning the processor to the preceding sleep state.
摘要翻译：使用新颖的连接待机睡眠状态降低处理器睡眠状态期间的功耗和耗散。在连接的待机休眠状态下，使用专用电源平面来维护处理器环境。为了节省电力，处理器上的不必要的组件被关闭，包括所有时钟组件，以及先前指向处理器的唤醒源被引导到平台控制中心。平台控制集线器在连接的待机睡眠状态期间维持处理器的某些架构功能，并且管理用于将处理器返回到先前睡眠状态的唤醒逻辑。

8. 发明授权

US09274580B2 Voltage regulator supplying power exclusively to a non-core region of a processor having a supply capability threshold 有权
标题翻译：电压调节器专门提供具有供应能力阈值的处理器的非核心区域
公开(公告)号：US09274580B2
公开(公告)日：2016-03-01
申请号：US13537319
申请日：2012-06-29
申请人： Ruoying Mary Ma , Craig Forbell , Soethiha Soe , Jawad Haj-Yihia , Jeffrey Carlson
发明人： Ruoying Mary Ma , Craig Forbell , Soethiha Soe , Jawad Haj-Yihia , Jeffrey Carlson
IPC分类号： G06F1/00 , G06F11/30 , G06F1/28 , G06F1/32 , G06F1/26 , G06F1/30
CPC分类号： G06F1/28 , G06F1/26 , G06F1/30 , G06F1/3203
摘要： Systems and methods may provide for monitoring a current provided from a voltage regulator to a non-core region of a processor, and asserting a throttle signal to the non-core region of the processor if the current exceeds a supply capability threshold of the voltage regulator. In one example, a specified current supply capability of the non-core region is greater than a current supply capability of the voltage regulator, and the supply capability threshold is less than the specified current supply capability of the non-core region and an over current protection threshold of the non-core region.
摘要翻译：系统和方法可以提供监视从电压调节器提供给处理器的非核心区域的电流，以及如果电流超过电压调节器的供应能力阈值，则将该节气门信号断言到处理器的非核心区域。在一个示例中，非核心区域的指定电流供应能力大于电压调节器的电流供应能力，并且供电能力阈值小于非核心区域的指定电流供应能力和过电流非核心区域的保护阈值。

9. 发明申请

US20140181352A1 INTERCONNECT TO COMMUNICATE INFORMATION UNI-DIRECTIONALLY 有权
标题翻译：不间断地传播信息
公开(公告)号：US20140181352A1
公开(公告)日：2014-06-26
申请号：US13727052
申请日：2012-12-26
申请人： Shaun M. Conrad , William Knolla , Douglas R. Moran , SM M. RAHMAN , JAWAD HAJ-YIHIA , ALON NAVEH , OHAD FALIK
发明人： Shaun M. Conrad , William Knolla , Douglas R. Moran , SM M. RAHMAN , JAWAD HAJ-YIHIA , ALON NAVEH , OHAD FALIK
IPC分类号： G06F13/40 , G06F1/32
CPC分类号： G06F1/3206 , G06F1/3237 , G06F1/324 , G06F1/3296 , G06F13/40 , G06F13/4027 , G06F13/4068 , Y02D10/126 , Y02D10/128 , Y02D10/151 , Y02D10/172
摘要： A processor includes at least one core, a power control unit, and a first interconnect to couple with a peripheral controller. The first interconnect is to provide a first uni-directional communication path for communication of first power management data from the processor to the peripheral controller. Other embodiments are described and claimed.
摘要翻译：处理器包括至少一个核心，功率控制单元和与外围控制器耦合的第一互连。第一互连是提供用于从处理器到外围控制器的第一电力管理数据的通信的第一单向通信路径。描述和要求保护其他实施例。

10. 发明申请

US20140095911A1 Controlling Power Consumption By Power Management Link 有权
标题翻译：通过电源管理链路控制功耗
公开(公告)号：US20140095911A1
公开(公告)日：2014-04-03
申请号：US13631907
申请日：2012-09-29
申请人： Nir Rosenzweig , Efraim Rotem , Jawad Haj-Yihia , Ohad Falik
发明人： Nir Rosenzweig , Efraim Rotem , Jawad Haj-Yihia , Ohad Falik
IPC分类号： G06F1/32
CPC分类号： G06F1/3296 , G06F1/3203 , G06F1/3209 , G06F1/3215 , G06F1/3287 , Y02D10/171
摘要： Methods and apparatus relating to controlling power consumption by a power management link are described. In one embodiment, the physical interface of a power management (PM) link is shut down when a processor is in a sleep state (e.g., to conserve power), while maintaining the availability of the processor for communication to a (e.g., embedded) controller over the PM link. Other embodiments are also disclosed and claimed.
摘要翻译：描述了通过电力管理链路控制电力消耗的方法和装置。在一个实施例中，当处理器处于休眠状态（例如，以节省功率）时，功率管理（PM）链路的物理接口被关闭，同时保持用于通信的处理器的可用性（例如，嵌入式）控制器通过PM链路。还公开并要求保护其他实施例。

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