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1. 发明授权

US06934656B2 Auto-linking of function logic state with testcase regression list 失效
标题翻译：功能逻辑状态与测试案例回归列表的自动链接
公开(公告)号：US06934656B2
公开(公告)日：2005-08-23
申请号：US10605884
申请日：2003-11-04
申请人： Jason Michael Norman , Nancy H. Pratt , Sebastian Theodore Ventrone
发明人： Jason Michael Norman , Nancy H. Pratt , Sebastian Theodore Ventrone
IPC分类号： G01R31/14 , G06F11/26
CPC分类号： G06F11/261
摘要： A method and system for identifying logic function areas, which make up a virtual machine, that are affected by specific testcases. A Hardware Descriptor Language (HDL) is used to create a software model of the virtual machine. A simulator compiles and analyzes the HDL model, and creates a matrix scoreboard identifying logic function areas in the virtual machine. A complete list of testcases is run on the virtual machine while a monitor correlates each testcase with affected logic function areas to fill in the matrix scoreboard. When a subsequent test failure occurs, either because of a modification to a logic function area, or the execution of a new test, all logic function areas that are affected, either directly or indirectly, are identified.
摘要翻译：用于识别构成虚拟机的逻辑功能区域受到特定测试用例影响的方法和系统。硬件描述符语言（HDL）用于创建虚拟机的软件模型。模拟器编译和分析HDL模型，并创建一个标识虚拟机中逻辑功能区域的矩阵记分板。测试用例的完整列表在虚拟机上运行，而监视器将每个测试用例与受影响的逻辑功能区域相关联，以填充矩阵记分板。当随后的测试失败发生时，由于对逻辑功能区域的修改或新测试的执行，所有被直接或间接影响的逻辑功能区域都被识别。

2. 发明申请

US20080183941A1 HARDWARE ASSISTED BUS STATE TRANSITION USING CONTENT ADDRESSABLE MEMORIES. 审中-公开
标题翻译：硬件辅助总线状态转换使用内容可寻址的记忆。
公开(公告)号：US20080183941A1
公开(公告)日：2008-07-31
申请号：US11627588
申请日：2007-01-26
申请人： Serafino Bueti , Kenneth Joseph Goodnow , Todd Edwin Leonard , Gregory John Mann , Jason Michael Norman , Clarence Rosser Ogilvie , Peter Anthony Sandon , Charles S. Woodruff
发明人： Serafino Bueti , Kenneth Joseph Goodnow , Todd Edwin Leonard , Gregory John Mann , Jason Michael Norman , Clarence Rosser Ogilvie , Peter Anthony Sandon , Charles S. Woodruff
IPC分类号： G06F3/00
CPC分类号： G06F13/4059
摘要： A universal peripheral processor architecture on an integrated circuit (IC) includes a first data bus and a second data bus communicating with first and second ternary content addressable memory (TCAM) devices configured as state machines. First and second processors are coupled to the first bus interface logic and the second bus interface logic. First and second data storage devices communicate with the first and second processors and are coupled to the first and second data buses and communicate with each other. The TCAM devices are configured as state machines and are coupled to and adapted to interface with the processors, the data storage devices, and the bus interface logic using predefined protocols.
摘要翻译：集成电路（IC）上的通用外围处理器架构包括与配置为状态机的第一和第二三进制内容可寻址存储器（TCAM）设备通信的第一数据总线和第二数据总线。第一和第二处理器耦合到第一总线接口逻辑和第二总线接口逻辑。第一和第二数据存储设备与第一和第二处理器进行通信，并且耦合到第一和第二数据总线并彼此通信。 TCAM设备被配置为状态机，并且使用预定义的协议耦合到并适于与处理器，数据存储设备和总线接口逻辑的接口。

3. 发明授权

US08347019B2 Structure for hardware assisted bus state transition circuit using content addressable memories 失效
标题翻译：使用内容可寻址存储器的硬件辅助总线状态转换电路的结构
公开(公告)号：US08347019B2
公开(公告)日：2013-01-01
申请号：US12122321
申请日：2008-05-16
申请人： Serafino Bueti , Kenneth Joseph Goodnow , Todd Edwin Leonard , Gregory John Mann , Jason Michael Norman , Clarence Rosser Ogilvie , Peter Anthony Sandon , Charles S. Woodruff
发明人： Serafino Bueti , Kenneth Joseph Goodnow , Todd Edwin Leonard , Gregory John Mann , Jason Michael Norman , Clarence Rosser Ogilvie , Peter Anthony Sandon , Charles S. Woodruff
IPC分类号： G06F3/00 , G06F13/00
CPC分类号： G06F13/4059
摘要： A design structure including universal peripheral processor architecture on an integrated circuit (IC) includes a first data bus and a second data bus communicating with first and second ternary content addressable memory (TCAM) devices configured as state machines. First and second processors are coupled to the first bus interface logic and the second bus interface logic. First and second data storage devices communicate with the first and second processors and are coupled to the first and second data buses and communicate with each other. The TCAM devices are configured as state machines and are coupled to and adapted to interface with the processors, the data storage devices, and the bus interface logic using predefined protocols.
摘要翻译：包括集成电路（IC）上的通用外围处理器架构的设计结构包括与配置为状态机的第一和第二三进制内容可寻址存储器（TCAM）设备通信的第一数据总线和第二数据总线。第一和第二处理器耦合到第一总线接口逻辑和第二总线接口逻辑。第一和第二数据存储设备与第一和第二处理器进行通信，并且耦合到第一和第二数据总线并彼此通信。 TCAM设备被配置为状态机，并且使用预定义的协议耦合到并适于与处理器，数据存储设备和总线接口逻辑的接口。

4. 发明申请

US20080282015A1 DESIGN STRUCTURE FOR HARDWARE ASSISTED BUS STATE TRANSITION CIRCUIT USING CONTENT ADDRESSABLE MEMORIES 失效
标题翻译：硬件辅助总线转换电路使用内部可寻址存储器的设计结构
公开(公告)号：US20080282015A1
公开(公告)日：2008-11-13
申请号：US12122321
申请日：2008-05-16
申请人： Serafino Bueti , Kenneth Joseph Goodnow , Todd Edwin Leonard , Gregory John Mann , Jason Michael Norman , Clarence Rosser Ogilvie , Peter Anthony Sandon , Charles S. Woodruff
发明人： Serafino Bueti , Kenneth Joseph Goodnow , Todd Edwin Leonard , Gregory John Mann , Jason Michael Norman , Clarence Rosser Ogilvie , Peter Anthony Sandon , Charles S. Woodruff
IPC分类号： G06F13/40
CPC分类号： G06F13/4059
摘要： A design structure including universal peripheral processor architecture on an integrated circuit (IC) includes a first data bus and a second data bus communicating with first and second ternary content addressable memory (TCAM) devices configured as state machines. First and second processors are coupled to the first bus interface logic and the second bus interface logic. First and second data storage devices communicate with the first and second processors and are coupled to the first and second data buses and communicate with each other. The TCAM devices are configured as state machines and are coupled to and adapted to interface with the processors, the data storage devices, and the bus interface logic using predefined protocols.
摘要翻译：包括集成电路（IC）上的通用外围处理器架构的设计结构包括与配置为状态机的第一和第二三进制内容可寻址存储器（TCAM）设备通信的第一数据总线和第二数据总线。第一和第二处理器耦合到第一总线接口逻辑和第二总线接口逻辑。第一和第二数据存储设备与第一和第二处理器进行通信，并且耦合到第一和第二数据总线并彼此通信。 TCAM设备被配置为状态机，并且使用预定义的协议耦合到并适于与处理器，数据存储设备和总线接口逻辑的接口。

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