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1. 发明授权

US08176257B2 Cache used both as cache and staging buffer 有权
标题翻译：缓存用作缓存和分段缓冲区
公开(公告)号：US08176257B2
公开(公告)日：2012-05-08
申请号：US13087974
申请日：2011-04-15
申请人： Ruchi Wadhawan , Jason M. Kassoff , George Kong Yiu
发明人： Ruchi Wadhawan , Jason M. Kassoff , George Kong Yiu
IPC分类号： G06F13/00 , G06F12/00
CPC分类号： G06F12/0802 , G06F12/0835 , G06F12/12
摘要： In one embodiment, a cache comprises a data memory comprising a plurality of data entries, each data entry having capacity to store a cache block of data, and a cache control unit coupled to the data memory. The cache control unit is configured to dynamically allocate a given data entry in the data memory to store a cache block being cached or to store data that is not being cache but is being staged for retransmission on an interface to which the cache is coupled.
摘要翻译：在一个实施例中，高速缓存包括包括多个数据条目的数据存储器，每个数据条目具有存储高速缓存数据块的能力，以及耦合到数据存储器的高速缓存控制单元。高速缓存控制单元被配置为动态地分配数据存储器中的给定数据条目以存储被缓存的高速缓存块，或者存储不是高速缓存的数据，而是正在高速缓存耦合到的接口上进行重传。

2. 发明申请

US20130132682A1 Push Mechanism for Quality of Service (QoS) Support in Coherency Port 有权
标题翻译：推送机制在服务质量（QoS）支持一致性端口
公开(公告)号：US20130132682A1
公开(公告)日：2013-05-23
申请号：US13300886
申请日：2011-11-21
申请人： Jason M. Kassoff
发明人： Jason M. Kassoff
IPC分类号： G06F12/08
CPC分类号： G06F13/1684
摘要： In an embodiment, a memory port controller (MPC) is coupled to a memory port and receives transactions from processors and a coherency port (ACP) used by one or more peripheral devices that may be cache coherent. The transactions include various QoS parameters. If a high priority QoS transaction is received on the ACP, the MPC may push previous (lower priority) transactions until the high priority transaction may be completed. The MPC may maintain a count of outstanding high priority QoS transactions. The L2 interface controller and ACP controller may push increment and decrement events based on processing the high priority QoS transactions, and the MPC may push the memory transactions when the count is non-zero. In an embodiment, the MPC may continue pushing transactions until the L2 interface controller informs the MPC that the earlier transactions have been completed (e.g. by passing an upgrade token to the MPC).
摘要翻译：在一个实施例中，存储器端口控制器（MPC）耦合到存储器端口并且接收来自处理器的事务和由一个或多个外围设备使用的可能是高速缓存一致的一致性端口（ACP）。交易包括各种QoS参数。如果在ACP上接收到高优先级的QoS事务，则MPC可以推动先前（较低优先级）事务，直到高优先级事务可以完成。 MPC可以保持未完成的高优先级QoS事务的计数。 L2接口控制器和ACP控制器可以基于处理高优先级QoS事务来推动递减事件，并且当计数不为零时，MPC可以推动存储器事务。在一个实施例中，MPC可以继续推送事务，直到L2接口控制器通知MPC早先的事务已经完成（例如通过将升级令牌传递给MPC）。

3. 发明授权

US07949829B2 Cache used both as cache and staging buffer 有权
标题翻译：缓存用作缓存和分段缓冲区
公开(公告)号：US07949829B2
公开(公告)日：2011-05-24
申请号：US12566609
申请日：2009-09-24
申请人： Ruchi Wadhawan , Jason M. Kassoff , George Kong Yiu
发明人： Ruchi Wadhawan , Jason M. Kassoff , George Kong Yiu
IPC分类号： G06F13/00 , G06F12/00
CPC分类号： G06F12/0802 , G06F12/0835 , G06F12/12
摘要： In one embodiment, a cache comprises a data memory comprising a plurality of data entries, each data entry having capacity to store a cache block of data, and a cache control unit coupled to the data memory. The cache control unit is configured to dynamically allocate a given data entry in the data memory to store a cache block being cached or to store data that is not being cache but is being staged for retransmission on an interface to which the cache is coupled.
摘要翻译：在一个实施例中，高速缓存包括包括多个数据条目的数据存储器，每个数据条目具有存储高速缓存数据块的能力，以及耦合到数据存储器的高速缓存控制单元。高速缓存控制单元被配置为动态地分配数据存储器中的给定数据条目以存储被缓存的高速缓存块，或者存储不是高速缓存的数据，而是正在高速缓存耦合到的接口上进行重传。

4. 发明授权

US08719506B2 Push mechanism for quality of service (QoS) support in coherency port 有权
标题翻译：一致性端口的服务质量（QoS）支持推送机制
公开(公告)号：US08719506B2
公开(公告)日：2014-05-06
申请号：US13300886
申请日：2011-11-21
申请人： Jason M. Kassoff
发明人： Jason M. Kassoff
IPC分类号： G06F12/08
CPC分类号： G06F13/1684
摘要： In an embodiment, a memory port controller (MPC) is coupled to a memory port and receives transactions from processors and a coherency port (ACP) used by one or more peripheral devices that may be cache coherent. The transactions include various quality of service (QoS) parameters. If a high priority QoS transaction is received on the ACP, the MPC may push previous (lower priority) transactions until the high priority transaction may be completed. The MPC may maintain a count of outstanding high priority QoS transactions. The L2 interface controller and ACP controller may push increment and decrement events based on processing the high priority QoS transactions, and the MPC may push the memory transactions when the count is non-zero. In an embodiment, the MPC may continue pushing transactions until the L2 interface controller informs the MPC that the earlier transactions have been completed.
摘要翻译：在一个实施例中，存储器端口控制器（MPC）耦合到存储器端口并且接收来自处理器的事务和由一个或多个外围设备使用的可能是高速缓存一致的一致性端口（ACP）。交易包括各种服务质量（QoS）参数。如果在ACP上接收到高优先级的QoS事务，则MPC可以推动先前（较低优先级）事务，直到高优先级事务可以完成。 MPC可以保持未完成的高优先级QoS事务的计数。 L2接口控制器和ACP控制器可以基于处理高优先级QoS事务来推动递减事件，并且当计数不为零时，MPC可以推动存储器事务。在一个实施例中，MPC可以继续推送事务，直到L2接口控制器通知MPC早先的事务已经完成。

5. 发明申请

US20110296110A1 Critical Word Forwarding with Adaptive Prediction 有权
标题翻译：关键词转发与自适应预测
公开(公告)号：US20110296110A1
公开(公告)日：2011-12-01
申请号：US12791387
申请日：2010-06-01
申请人： Brian P. Lilly , Jason M. Kassoff , Hao Chen
发明人： Brian P. Lilly , Jason M. Kassoff , Hao Chen
IPC分类号： G06F12/00 , G06F12/08 , G06F1/12
CPC分类号： G06F13/1668 , G06F12/0862
摘要： In an embodiment, a system includes a memory controller, processors and corresponding caches. The system may include sources of uncertainty that prevent the precise scheduling of data forwarding for a load operation that misses in the processor caches. The memory controller may provide an early response that indicates that data should be provided in a subsequent clock cycle. An interface unit between the memory controller and the caches/processors may predict a delay from a currently-received early response to the corresponding data, and may speculatively prepare to forward the data assuming that it will be available as predicted. The interface unit may monitor the delays between the early response and the forwarding of the data, or at least the portion of the delay that may vary. Based on the measured delays, the interface unit may modify the subsequently predicted delays.
摘要翻译：在一个实施例中，系统包括存储器控制器，处理器和对应的高速缓存。该系统可以包括不确定性源，其阻止针对处理器高速缓存中丢失的加载操作的数据转发的精确调度。存储器控制器可以提供指示在随后的时钟周期中应该提供数据的早期响应。存储器控制器和高速缓存/处理器之间的接口单元可以预测从当前接收的早期响应到相应数据的延迟，并且可以推测地准备转发数据，假设它将如预期的那样可用。接口单元可以监视早期响应和数据转发之间的延迟，或至少可能变化的部分延迟。基于测量的延迟，接口单元可以修改随后预测的延迟。

6. 发明申请

US20110197033A1 Cache Used Both as Cache and Staging Buffer 有权
标题翻译：缓存用作缓存和分段缓冲区
公开(公告)号：US20110197033A1
公开(公告)日：2011-08-11
申请号：US13087974
申请日：2011-04-15
申请人： Ruchi Wadhawan , Jason M. Kassoff , George Kong Yiu
发明人： Ruchi Wadhawan , Jason M. Kassoff , George Kong Yiu
IPC分类号： G06F12/08
CPC分类号： G06F12/0802 , G06F12/0835 , G06F12/12
摘要： In one embodiment, a cache comprises a data memory comprising a plurality of data entries, each data entry having capacity to store a cache block of data, and a cache control unit coupled to the data memory. The cache control unit is configured to dynamically allocate a given data entry in the data memory to store a cache block being cached or to store data that is not being cache but is being staged for retransmission on an interface to which the cache is coupled.
摘要翻译：在一个实施例中，高速缓存包括包括多个数据条目的数据存储器，每个数据条目具有存储高速缓存数据块的能力，以及耦合到数据存储器的高速缓存控制单元。高速缓存控制单元被配置为动态地分配数据存储器中的给定数据条目以存储被缓存的高速缓存块，或者存储不是高速缓存的数据，而是正在高速缓存耦合到的接口上进行重传。

7. 发明授权

US08769332B2 Regional clock gating and dithering 有权
标题翻译：区域时钟选通和抖动
公开(公告)号：US08769332B2
公开(公告)日：2014-07-01
申请号：US13355023
申请日：2012-01-20
申请人： Conrad H. Ziesler , John H. Mylius , Jason M. Kassoff
发明人： Conrad H. Ziesler , John H. Mylius , Jason M. Kassoff
IPC分类号： G06F1/00 , H03K19/00
CPC分类号： G06F1/10 , G06F1/3237 , H03K19/0016 , Y02D10/128
摘要： A system and method for dithering a clock signal during idle times is disclosed. An integrated circuit (IC) includes a number of functional units and a clock tree. The clock tree includes a root level clock-gating circuit, a number of regional clock-gating circuits, and a number of leaf level clock-gating circuits. The root level clock-gating circuit is coupled to distribute an operating clock signal to the regional clock-gating circuits, while the regional clock-gating circuits are each configured to distribute the operating clock signal to correspondingly coupled ones of the leaf level clock-gating circuits. The IC may further include a control unit configured to monitor activity levels and indications from each of the functional units. The control unit may cause the root clock-gating circuit to dither the clock signal if the IC is idle, wherein dithering includes reducing the duty cycle and the effective frequency of the operating clock signal.
摘要翻译：公开了一种用于在空闲时间期间抖动时钟信号的系统和方法。集成电路（IC）包括多个功能单元和时钟树。时钟树包括根电平时钟门控电路，多个区域时钟门控电路和多个叶电平时钟门控电路。根电平时钟门控电路被耦合以将操作时钟信号分配给区域时钟门控电路，而区域时钟选通电路被配置为将操作时钟信号分配给对应的叶级别门控时钟信号电路。 IC还可以包括控制单元，其被配置为监视来自每个功能单元的活动水平和指示。如果IC空闲，则控制单元可以使根时钟选通电路对时钟信号进行抖动，其中抖动包括降低工作时钟信号的占空比和有效频率。

8. 发明授权

US08713277B2 Critical word forwarding with adaptive prediction 有权
标题翻译：关键词转发与自适应预测
公开(公告)号：US08713277B2
公开(公告)日：2014-04-29
申请号：US12791387
申请日：2010-06-01
申请人： Brian P. Lilly , Jason M. Kassoff , Hao Chen
发明人： Brian P. Lilly , Jason M. Kassoff , Hao Chen
IPC分类号： G06F12/00
CPC分类号： G06F13/1668 , G06F12/0862
摘要： In an embodiment, a system includes a memory controller, processors and corresponding caches. The system may include sources of uncertainty that prevent the precise scheduling of data forwarding for a load operation that misses in the processor caches. The memory controller may provide an early response that indicates that data should be provided in a subsequent clock cycle. An interface unit between the memory controller and the caches/processors may predict a delay from a currently-received early response to the corresponding data, and may speculatively prepare to forward the data assuming that it will be available as predicted. The interface unit may monitor the delays between the early response and the forwarding of the data, or at least the portion of the delay that may vary. Based on the measured delays, the interface unit may modify the subsequently predicted delays.
摘要翻译：在一个实施例中，系统包括存储器控制器，处理器和对应的高速缓存。该系统可以包括不确定性源，其阻止针对处理器高速缓存中丢失的加载操作的数据转发的精确调度。存储器控制器可以提供指示在随后的时钟周期中应该提供数据的早期响应。存储器控制器和高速缓存/处理器之间的接口单元可以预测从当前接收的早期响应到相应数据的延迟，并且可以推测地准备转发数据，假设它将如预期的那样可用。接口单元可以监视早期响应和数据转发之间的延迟，或至少可能变化的部分延迟。基于测量的延迟，接口单元可以修改随后预测的延迟。

9. 发明授权

US07624235B2 Cache used both as cache and staging buffer 有权
标题翻译：缓存用作缓存和分段缓冲区
公开(公告)号：US07624235B2
公开(公告)日：2009-11-24
申请号：US11565391
申请日：2006-11-30
申请人： Ruchi Wadhawan , Jason M. Kassoff , George Kong Yiu
发明人： Ruchi Wadhawan , Jason M. Kassoff , George Kong Yiu
IPC分类号： G06F13/00 , G06F12/00
CPC分类号： G06F12/0802 , G06F12/0835 , G06F12/12
摘要： In one embodiment, a cache comprises a data memory comprising a plurality of data entries, each data entry having capacity to store a cache block of data, and a cache control unit coupled to the data memory. The cache control unit is configured to dynamically allocate a given data entry in the data memory to store a cache block being cached or to store data that is not being cache but is being staged for retransmission on an interface to which the cache is coupled.
摘要翻译：在一个实施例中，高速缓存包括包括多个数据条目的数据存储器，每个数据条目具有存储高速缓存数据块的能力，以及耦合到数据存储器的高速缓存控制单元。高速缓存控制单元被配置为动态地分配数据存储器中的给定数据条目以存储被缓存的高速缓存块，或者存储不是高速缓存的数据，而是正在高速缓存耦合到的接口上进行重传。

10. 发明申请

US20130191677A1 Regional Clock Gating and Dithering 有权
标题翻译：区域时钟门控和抖动
公开(公告)号：US20130191677A1
公开(公告)日：2013-07-25
申请号：US13355023
申请日：2012-01-20
申请人： Conrad H. Ziesler , John H. Mylius , Jason M. Kassoff
发明人： Conrad H. Ziesler , John H. Mylius , Jason M. Kassoff
IPC分类号： G06F1/10 , H03K3/017
CPC分类号： G06F1/10 , G06F1/3237 , H03K19/0016 , Y02D10/128
摘要： A system and method for dithering a clock signal during idle times is disclosed. An integrated circuit (IC) includes a number of functional units and a clock tree. The clock tree includes a root level clock-gating circuit, a number of regional clock-gating circuits, and a number of leaf level clock-gating circuits. The root level clock-gating circuit is coupled to distribute an operating clock signal to the regional clock-gating circuits, while the regional clock-gating circuits are each configured to distribute the operating clock signal to correspondingly coupled ones of the leaf level clock-gating circuits. The IC may further include a control unit configured to monitor activity levels and indications from each of the functional units. The control unit may cause the root clock-gating circuit to dither the clock signal if the IC is idle, wherein dithering includes reducing the duty cycle and the effective frequency of the operating clock signal.
摘要翻译：公开了一种用于在空闲时间期间抖动时钟信号的系统和方法。集成电路（IC）包括多个功能单元和时钟树。时钟树包括根电平时钟门控电路，多个区域时钟门控电路和多个叶电平时钟门控电路。根电平时钟门控电路被耦合以将操作时钟信号分配给区域时钟门控电路，而区域时钟门控电路各自被配置为将操作时钟信号分配给对应的叶级别门控时钟信号电路。 IC还可以包括控制单元，其被配置为监视来自每个功能单元的活动水平和指示。如果IC空闲，则控制单元可以使根时钟选通电路对时钟信号进行抖动，其中抖动包括降低工作时钟信号的占空比和有效频率。

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