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1. 发明授权

US5375214A Single translation mechanism for virtual storage dynamic address translation with non-uniform page sizes 失效
标题翻译：具有非均匀页面大小的虚拟存储动态地址转换的单一翻译机制
公开(公告)号：US5375214A
公开(公告)日：1994-12-20
申请号：US192768
申请日：1994-02-07
申请人： Jamshed H. Mirza , Steven W. White
发明人： Jamshed H. Mirza , Steven W. White
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , G06F2212/652
摘要： A dynamic address translation mechanism uses a single translation look aside buffer (TLB) facility for pages of various sizes. The single TLB is supported by a small amount of special hardware. This hardware includes logic for detecting a page size prior to translation and generating a mask. The logic selects a set of virtual address bits for addressing the entries in the TLB. Parts of the virtual address are masked and merged with the address read out of the TLB to form the real address.
摘要翻译：动态地址转换机制对于各种尺寸的页面使用单个翻译看缓冲（TLB）设施。单个TLB由少量特殊硬件支持。该硬件包括用于在翻译之前检测页面大小并产生掩码的逻辑。该逻辑选择一组虚拟地址位来寻址TLB中的条目。虚拟地址的部分被屏蔽并与从TLB读出的地址合并形成真实的地址。

2. 发明授权

US5247645A Dynamic memory mapper which supports interleaving across 2.sup.N +1, 2.sup. N .sup.N -1 number of banks for reducing contention during nonunit stride accesses 失效
标题翻译：动态存储器映射，支持跨越2N + 1，2N和2N-1的数量，用于在非逻辑连接访问期间减少内容的银行数量
公开(公告)号：US5247645A
公开(公告)日：1993-09-21
申请号：US668007
申请日：1991-03-12
申请人： Jamshed H. Mirza , Steven W. White
发明人： Jamshed H. Mirza , Steven W. White
IPC分类号： G06F12/16 , G11C29/00
CPC分类号： G11C29/76 , G11C29/88
摘要： A memory system for a high performance data processing system comprises a plurality of memory modules. In the preferred embodiment, there are 2.sup.N +1 memory modules. In a specific example, there are 65 such modules. When all 65 modules are enabled, a real-to-physical translation unit generates logical module addresses from 0 to 64 using modulo 65 calculations. Once a module failure is detected, the translation unit maps the real addresses to logical module addresses from 0 to 63 by performing modulo 64 calculations. The contiguous set of logical module addresses are then mapped to a set of physical module addresses which do not include the failed module.

3. 发明授权

US06111894A Hardware interface between a switch adapter and a communications subsystem in a data processing system 失效
标题翻译：交换适配器与数据处理系统中的通信子系统之间的硬件接口
公开(公告)号：US06111894A
公开(公告)日：2000-08-29
申请号：US920084
申请日：1997-08-26
申请人： Carl A. Bender , Paul D. DiNicola , Kevin J. Gildea , Rama K. Govindaraju , Chulho Kim , Jamshed H. Mirza , Gautam H. Shah
发明人： Carl A. Bender , Paul D. DiNicola , Kevin J. Gildea , Rama K. Govindaraju , Chulho Kim , Jamshed H. Mirza , Gautam H. Shah
IPC分类号： H04L29/06 , G06F3/00
CPC分类号： H04L29/06 , H04L69/161 , H04L69/164 , H04L69/16
摘要： Method, apparatus and program product for communicating from a node to a communications device. A Hardware Abstraction Layer (HAL) provides functions which can be called from user space in a node to access the communications device. An instance of HAL is created in the node. Device specific characteristics from the communications device and a pointer pointing to HAL functions for accessing the communications device are obtained by HAL. HAL then opens multiple ports on the communications device using the functions pointed to by the pointer, and messages are sent between the node and the communications device. The messages thus sent are optimized with respect to the communications device as determined by the obtained device specific characteristics. Multiple processes and protocol stacks may be associated with each port in a single instance of HAL. A further embodiment provides that multiple virtual ports may be associated with a port, with a multiple protocol stacks associated with each virtual port. A further embodiment provides that multiple communications devices may be associated with a single instance of HAL.
摘要翻译：用于从节点到通信设备进行通信的方法，装置和程序产品。硬件抽象层（HAL）提供可从节点中的用户空间调用以访问通信设备的功能。在节点中创建HAL的一个实例。来自通信设备的设备特定特征和指向HAL功能的指针用于访问通信设备，由HAL获得。然后，HAL使用指针指向的功能在通信设备上打开多个端口，并且在节点和通信设备之间发送消息。如此发送的消息相对于通过所获得的设备特定特性确定的通信设备进行了优化。多个进程和协议栈可能与HAL的单个实例中的每个端口相关联。另一实施例提供了多个虚拟端口可以与端口相关联，其中多个协议栈与每个虚拟端口相关联。另一实施例提供多个通信设备可以与HAL的单个实例相关联。

4. 发明授权

US6070189A Signaling communication events in a computer network 失效
标题翻译：在计算机网络中进行信令通信事件
公开(公告)号：US6070189A
公开(公告)日：2000-05-30
申请号：US921757
申请日：1997-08-26
申请人： Carl A. Bender , Paul D. DiNicola , Kevin J. Gildea , Rama K. Govindaraju , Chulho Kim , Jamshed H. Mirza , Gautam H. Shah , Jaroslaw Nieplocha
发明人： Carl A. Bender , Paul D. DiNicola , Kevin J. Gildea , Rama K. Govindaraju , Chulho Kim , Jamshed H. Mirza , Gautam H. Shah , Jaroslaw Nieplocha
IPC分类号： G06F9/46 , G06F15/173 , G06F13/00
CPC分类号： G06F9/542 , G06F15/17375
摘要： A method, apparatus and program product for detecting a communication event in a distributed parallel data processing system in which a message is sent from an origin to a target. A low-level application programming interface (LAPI) is provided which has an operation for associating a counter with a communication event to be detected. The LAPI increments the counter upon the occurrence of the communication event. The number in the counter is monitored, and when the number increases, the event is detected. A completion counter in the origin is associated with the completion of a message being sent from the origin to the target. When the message is completed, LAPI increments the completion counter such that monitoring the completion counter detects the completion of the message. The completion counter may be used to insure that a first message has been sent from the origin to the target and completed before a second message is sent.
摘要翻译：一种用于检测分布式并行数据处理系统中的通信事件的方法，装置和程序产品，其中消息从原点发送到目标。提供了一种低级应用编程接口（LAPI），其具有将计数器与要检测的通信事件相关联的操作。 LAPI在通信事件发生时增加计数器。监视计数器中的数字，当数量增加时，检测到事件。原点的完成计数器与从原点发送到目标的消息的完成相关联。当消息完成时，LAPI会增加完成计数器，以便监视完成计数器检测到消息的完成。完成计数器可用于确保第一消息已经从原点发送到目标并且在发送第二消息之前完成。

5. 发明授权

US5625793A Automatic cache bypass for instructions exhibiting poor cache hit ratio 失效
标题翻译：自动缓存旁路，用于显示较差的缓存命中率的指令
公开(公告)号：US5625793A
公开(公告)日：1997-04-29
申请号：US685583
申请日：1991-04-15
申请人： Jamshed H. Mirza
发明人： Jamshed H. Mirza
IPC分类号： G06F9/38 , G06F12/08 , G06F17/16 , G06F12/12
CPC分类号： G06F9/383 , G06F12/0888
摘要： A cache bypass mechanism automatically avoids caching of data for instructions whose data references, for whatever reason, exhibit low cache hit ratio. The mechanism keeps a record of an instruction's behavior in the immediate past, and this record is used to decide whether its future references should be cached or not. If an instruction is experiencing bad cache hit ratio, it is marked as non-cacheable, and its data references are made to bypass the cache. This avoids the additional penalty of unnecessarily fetching the remaining words in the line, reduces the demand on the memory bandwidth, avoids flushing the cache of useful data and, in parallel processing environments, prevents line thrashing. The cache management scheme is automatic and requires no compiler or user intervention.
摘要翻译：缓存旁路机制可以自动避免对数据缓存数据，因为无论什么原因，数据引用都会显示低缓存命中率。该机制保持了一个指令在过去的行为的记录，并且该记录用于决定其未来的引用是否应被缓存。如果指令遇到不良缓存命中率，则会将其标记为不可缓存，并将其数据引用绕过缓存。这避免了不必要地取出行中剩余单词的额外损失，减少了对存储器带宽的需求，避免了刷新有用数据的缓存，并且在并行处理环境中可以防止线路颠覆。缓存管理方案是自动的，不需要编译器或用户干预。

6. 发明授权

US5357618A Cache prefetch and bypass using stride registers 失效
标题翻译：缓存预取和旁路使用stride寄存器
公开(公告)号：US5357618A
公开(公告)日：1994-10-18
申请号：US686221
申请日：1991-04-15
申请人： Jamshed H. Mirza , Steven W. White
发明人： Jamshed H. Mirza , Steven W. White
IPC分类号： G06F9/32 , G06F9/312 , G06F9/345 , G06F9/38 , G06F12/08 , G06F13/14
CPC分类号： G06F9/30043 , G06F12/0862 , G06F9/30032 , G06F9/3013 , G06F9/3455 , G06F9/383 , G06F2212/6026 , G06F2212/6028 , G06F8/4442
摘要： A technique and a mechanism accurately determines the correct prefetch line for loops with strides of 1, N, or a combination of stride values. Stride registers are used to assist in prefetching. Furthermore, stride register values can be used to specify "cacheability" of data on an object by object basis to prevent "cache flushing". The compiler uses a new instruction, "MOVE GPR TO STRIDE REGISTER", prior to a loop to insert the "calculated stride value(s)" into the stride register(s) associated with the index register(s) which will be incremented by that stride value. At the end of the loop, a second new instruction, "CLEAR STRIDE REGISTER SET", is used to place a value of zero in all of the stride registers to inhibit prefetching of data which would most likely not be used. A zero value in the stride registers inhibits prefetching. Non-zero values in the stride registers clearly mark the execution of a loop, which is where prefetching makes the most sense. It also clearly indicates the correct offset from the current address to use in determining the prefetch address. Since the offset is dependent on the particular index register used in specifying the storage address, data for loops with multiple strides can be correctly prefetched. A hardware managed set of stride registers provides a subset of the benefits afforded by the software managed implementation.
摘要翻译：技术和机制准确地确定了具有1，N的步幅或步幅值的组合的循环的正确预取行。 Stride寄存器用于辅助预取。此外，可以使用步幅寄存器值来指定对象上的数据的“缓存”，以防止“缓存刷新”。在循环之前，编译器使用新的指令“MOVE GPR TO STRIDE REGISTER”，将“计算出的步幅值”插入到与索引寄存器相关联的步幅寄存器中，该寄存器将被递增那一步的价值。在循环结束时，第二个新指令“CLEAR STRIDE REGISTER SET”用于在所有的步幅寄存器中设置一个零值，以禁止最可能不使用的数据预取。步幅寄存器中的零值禁止预取。步进寄存器中的非零值清楚地标记循环的执行，这是预取最有意义的地方。它还清楚地指出了与确定预取地址时使用的当前地址的正确偏移。由于偏移取决于用于指定存储地址的特定索引寄存器，因此可以正确预取具有多个步长的循环的数据。硬件管理的步进寄存器集提供了软件管理实现提供的一些优点。

7. 发明授权

US6038604A Method and apparatus for efficient communications using active messages 失效
标题翻译：用于使用活动消息进行高效通信的方法和装置
公开(公告)号：US6038604A
公开(公告)日：2000-03-14
申请号：US918816
申请日：1997-08-26
申请人： Carl A. Bender , Paul D. DiNicola , Kevin J. Gildea , Rama K. Govindaraju , Chulho Kim , Jamshed H. Mirza , Gautam H. Shah
发明人： Carl A. Bender , Paul D. DiNicola , Kevin J. Gildea , Rama K. Govindaraju , Chulho Kim , Jamshed H. Mirza , Gautam H. Shah
IPC分类号： G06F9/46 , H04L29/06 , H04L29/08 , G06F13/00
CPC分类号： G06F9/546 , H04L29/06 , H04L67/40 , H04L69/26 , H04L69/329
摘要： A method, apparatus and program product for message communication in a distributed parallel data processing system. A user message is sent from a sender to a receiver. The user message contains user data and a pointer to a header handler routine. The header handler routine includes a first pointer to a target user buffer and a second pointer to a completion routine. When the user message is received, a low level application program interface (LAPI) is informed which invokes the header handler routines which returns the first and second pointers. LAPI then transfers the user data to the user buffer indicated by the header handler routine, and invokes the completion routine indicated by the header handler routine to complete the transfer of the user message to the receiver.
摘要翻译：一种用于分布式并行数据处理系统中消息通信的方法，装置和程序产品。用户消息从发送方发送到接收方。用户消息包含用户数据和指向头处理程序例程的指针。报头处理程序例程包括指向目标用户缓冲区的第一指针和指向完成例程的第二指针。当接收到用户消息时，通知低级应用程序接口（LAPI），调用返回第一和第二指针的报头处理程序例程。然后，LAPI将用户数据传送到由报头处理程序指示的用户缓冲器，并调用由报头处理程序指示的完成例程，以完成将用户消息传送到接收器。

8. 发明授权

US5475827A Dynamic look-aside table for multiple size pages 失效
标题翻译：用于多个大小页面的动态查看表
公开(公告)号：US5475827A
公开(公告)日：1995-12-12
申请号：US223366
申请日：1994-04-01
申请人： Jeffery Y. Lee , Jamshed H. Mirza , Robert J. Stanton, Jr.
发明人： Jeffery Y. Lee , Jamshed H. Mirza , Robert J. Stanton, Jr.
IPC分类号： G06F12/10
CPC分类号： G06F12/1036 , G06F2212/652 , G06F2212/681
摘要： A dynamic address translation (DAT) mechanism which supports virtual memory pages of different sizes with minimal hardware and design impact. The dynamic look-aside table (DLAT) is modified to allow the addition of a second page size to system architecture. In one approach, the DLAT is divided into two sections, one for small (4KB) pages and one for large (1MB) pages. A steering table indicates whether the segment last contained 4KB pages or a 1MB page. As each segment is translated by the DAT mechanism, the page size (1MB or 4KB) contained in the segment is known, and this information is used to select the address bus used for indexing the DLAT. In an alternative approach, the DLAT is not divided into sections; rather, it can interchangeably hold/test/select either of the two different formats in any entry. The steering table dynamically changes the way in which the DLAT is addressed and selects the bits of the entry to be used in the translation.
摘要翻译：动态地址转换（DAT）机制，支持不同大小的虚拟内存页面，最小的硬件和设计影响。动态看门狗表（DLAT）被修改为允许将第二页大小添加到系统架构。在一种方法中，DLAT被分为两部分，一部分用于小型（4KB）页面，另一个用于大型（1MB）页面。转向表指示该段最后是否包含4KB页面或1MB页面。由于每个段由DAT机制翻译，段中包含的页面大小（1MB或4KB）是已知的，并且该信息用于选择用于索引DLAT的地址总线。在另一种方法中，DLAT不分为几部分; 相反，它可以互换地保存/测试/选择任何条目中的两种不同格式之一。转向表动态地改变DLAT的寻址方式，并选择要在转换中使用的条目的位。

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