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1. 发明授权

US09306694B2 Clock signal synchronization among computers in a network 有权
标题翻译：网络中计算机之间的时钟信号同步
公开(公告)号：US09306694B2
公开(公告)日：2016-04-05
申请号：US13448785
申请日：2012-04-17
申请人： Daniel N. de Araujo , James T. Hanna , James O. Nicholson , Bruce J. Wilkie
发明人： Daniel N. de Araujo , James T. Hanna , James O. Nicholson , Bruce J. Wilkie
IPC分类号： H04J3/06 , H04L7/00
CPC分类号： H04J3/0688 , H04J3/0658 , H04L7/0008
摘要： Methods, apparatus, and computer program products are disclosed for clock signal synchronization among computers in a network, including designating, as a primary clock signal for all the computers in a network, a clock signal from one of the computers in the network; providing the primary clock signal, simultaneously and in parallel, from the computer whose clock signal is designated as the primary clock signal to all the other computers in the network; and providing the primary clock signal, simultaneously and in parallel, from each computer in the network to all computers in the network through multiplexers and phase locked loops, with the primary clock signal locked in phase across all the computers by a phase locked loop on each computer.
摘要翻译：公开了用于网络中的计算机之间的时钟信号同步的方法，装置和计算机程序产品，包括将来自网络中的一台计算机的时钟信号指定为网络中所有计算机的主时钟信号; 从时钟信号被指定为主时钟信号的计算机同时并行地提供主时钟信号给网络中的所有其他计算机; 并且通过多路复用器和锁相环将网络中的每台计算机同时并行地并行地提供主网络中的所有计算机的主时钟信号，其中主时钟信号通过每个计算机上的锁相环锁定在所有计算机上电脑。

2. 发明申请

US20120203933A1 Clock Signal Synchronization Among Computers In A Network 有权
标题翻译：网络计算机中的时钟信号同步
公开(公告)号：US20120203933A1
公开(公告)日：2012-08-09
申请号：US13448785
申请日：2012-04-17
申请人： Daniel N. de Araujo , James T. Hanna , James O. Nicholson , Bruce J. Wilkie
发明人： Daniel N. de Araujo , James T. Hanna , James O. Nicholson , Bruce J. Wilkie
IPC分类号： G06F1/12 , G06F15/16
CPC分类号： H04J3/0688 , H04J3/0658 , H04L7/0008
摘要： Methods, apparatus, and computer program products are disclosed for clock signal synchronization among computers in a network, including designating, as a primary clock signal for all the computers in a network, a clock signal from one of the computers in the network; providing the primary clock signal, simultaneously and in parallel, from the computer whose clock signal is designated as the primary clock signal to all the other computers in the network; and providing the primary clock signal, simultaneously and in parallel, from each computer in the network to all computers in the network through multiplexers and phase locked loops, with the primary clock signal locked in phase across all the computers by a phase locked loop on each computer.
摘要翻译：公开了用于网络中的计算机之间的时钟信号同步的方法，装置和计算机程序产品，包括将来自网络中的一台计算机的时钟信号指定为网络中所有计算机的主时钟信号; 从时钟信号被指定为主时钟信号的计算机同时并行地提供主时钟信号给网络中的所有其他计算机; 并且通过多路复用器和锁相环将网络中的每台计算机同时并行地并行地提供主网络中的所有计算机的主时钟信号，其中主时钟信号通过每个计算机上的锁相环锁定在所有计算机上电脑。

3. 发明授权

US4907150A Apparatus and method for suspending and resuming software applications on a computer 失效
标题翻译：用于在计算机上挂起和恢复软件应用程序的装置和方法
公开(公告)号：US4907150A
公开(公告)日：1990-03-06
申请号：US225570
申请日：1988-07-26
申请人： Ronald X. Arroyo , Michael N. Day , Jimmie D. Edrington , James T. Hanna , Gary T. Hunt , Steven T. Pancoast
发明人： Ronald X. Arroyo , Michael N. Day , Jimmie D. Edrington , James T. Hanna , Gary T. Hunt , Steven T. Pancoast
IPC分类号： G06F1/26 , G06F1/30 , G06F1/32 , G06F9/46 , G06F11/14
CPC分类号： G06F1/3246 , G06F1/26 , G06F1/30 , G06F1/3203 , G06F9/461 , G05B2219/34306 , G05B2219/34365 , G06F11/14 , Y02P70/163 , Y02P70/169
摘要： A method and apparatus for powering down a computer system while saving the state of the system at power down is disclosed. The system maintains the capability to suspend the execution of an application program operating on the system at any point and resuming execution of the application program at that same point at a later time. The time at which the system may be powered down and then powered back up again is totally arbitrary and depends only upon the user of the system. At the time the system is powered off, the contents of all active registers as well as the states of all I/O devices in the system are stored in a special save area of system memory. This special save area is provided with power during the suspended time in order to retain the state of the system at the time it was powered down. By using this special save suspend area, the main memory area of the system is available to any application programs independently of the system save memory requirements. Additionally, the system may be powered on and off under software control thereby providing the capability for unattended system operation using an alarm function.
摘要翻译：公开了一种在断电的同时节省系统状态的电源系统的方法和装置。该系统保持在任何时候暂停在系统上运行的应用程序的执行的能力，并在稍后的时间恢复该同一点处的应用程序的执行。系统可以关闭电源，然后重新上电的时间完全是任意的，并且仅取决于系统的用户。当系统断电时，所有活动寄存器的内容以及系统中所有I / O设备的状态都存储在系统内存的特殊保存区域中。这个特殊的保存区域在暂停时间内提供电源，以便在断电时保持系统的状态。通过使用这个特殊的保存挂起区域，系统的主存储区域可用于任何应用程序，独立于系统节省存储器要求。此外，系统可以在软件控制下通电和关断，从而提供使用报警功能进行无人值守系统操作的能力。

4. 发明授权

US08199695B2 Clock signal synchronization among computers in a network 有权
标题翻译：网络中计算机之间的时钟信号同步
公开(公告)号：US08199695B2
公开(公告)日：2012-06-12
申请号：US11733432
申请日：2007-04-10
申请人： Daniel N. de Araujo , James T. Hanna , James O. Nicholson , Bruce J. Wilkie
发明人： Daniel N. de Araujo , James T. Hanna , James O. Nicholson , Bruce J. Wilkie
IPC分类号： H04B1/7073
CPC分类号： H04J3/0688 , H04J3/0658 , H04L7/0008
摘要： Methods, apparatus, and computer program products are disclosed for clock signal synchronization among computers in a network, including designating, as a primary clock signal for all the computers in a network, a clock signal from one of the computers in the network; providing the primary clock signal, simultaneously and in parallel, from the computer whose clock signal is designated as the primary clock signal to all the other computers in the network; and providing the primary clock signal, simultaneously and in parallel, from each computer in the network to all computers in the network through multiplexers and phase locked loops, with the primary clock signal locked in phase across all the computers by a phase locked loop on each computer.
摘要翻译：公开了用于网络中的计算机之间的时钟信号同步的方法，装置和计算机程序产品，包括将来自网络中的一台计算机的时钟信号指定为网络中所有计算机的主时钟信号; 从时钟信号被指定为主时钟信号的计算机同时并行地提供主时钟信号给网络中的所有其他计算机; 并且通过多路复用器和锁相环将网络中的每台计算机同时并行地并行地提供主网络中的所有计算机的主时钟信号，其中主时钟信号通过每个计算机上的锁相环锁定在所有计算机上电脑。

5. 发明授权

US09122875B2 Trusted platform module data harmonization during trusted server rendevous 有权
标题翻译：受信任的平台模块数据在可信服务器集成期间进行协调
公开(公告)号：US09122875B2
公开(公告)日：2015-09-01
申请号：US11381237
申请日：2006-05-02
申请人： Steven A. Bade , Richard A. Dayan , James T. Hanna , Andrew G. Kegel
发明人： Steven A. Bade , Richard A. Dayan , James T. Hanna , Andrew G. Kegel
IPC分类号： G06F21/57
CPC分类号： G06F21/57 , G06F21/575 , H04L2463/101
摘要： Embodiments of the present invention address deficiencies of the art in respect to trusted platform module (TPM) unification in a trusted computing environment and provide a novel and non-obvious method, system and computer program product for trusted platform module data harmonization. In one embodiment of the invention, a TPM log harmonization method can include designating both a single master TPM for a master node among multiple nodes, and also a multiplicity of subsidiary TPMs for remaining ones of the nodes. The method further can include extending the single master TPM with a measurement representing a rendezvous operation for the nodes.
摘要翻译：本发明的实施例解决了可信计算环境中可信任平台模块（TPM）统一方面的技术缺陷，并提供了一种用于可信平台模块数据协调的新颖且非显而易见的方法，系统和计算机程序产品。在本发明的一个实施例中，TPM对数协调方法可以包括指定多个节点之间的主节点的单个主TPM，以及用于剩余节点的多个辅助TPM。该方法还可以包括使用表示节点的会合操作的测量来扩展单个主TPM。

6. 发明申请

US20080256262A1 Clock Signal Synchronization Among Computers In A Network 有权
标题翻译：网络计算机中的时钟信号同步
公开(公告)号：US20080256262A1
公开(公告)日：2008-10-16
申请号：US11733432
申请日：2007-04-10
申请人： Daniel N. de Araujo , James T. Hanna , James O. Nicholson , Bruce J. Wilkie
发明人： Daniel N. de Araujo , James T. Hanna , James O. Nicholson , Bruce J. Wilkie
IPC分类号： G06F15/16
CPC分类号： H04J3/0688 , H04J3/0658 , H04L7/0008
摘要： Methods, apparatus, and computer program products are disclosed for clock signal synchronization among computers in a network, including designating, as a primary clock signal for all the computers in a network, a clock signal from one of the computers in the network; providing the primary clock signal, simultaneously and in parallel, from the computer whose clock signal is designated as the primary clock signal to all the other computers in the network; and providing the primary clock signal, simultaneously and in parallel, from each computer in the network to all computers in the network through multiplexers and phase locked loops, with the primary clock signal locked in phase across all the computers by a phase locked loop on each computer.
摘要翻译：公开了用于网络中的计算机之间的时钟信号同步的方法，装置和计算机程序产品，包括将来自网络中的一台计算机的时钟信号指定为网络中所有计算机的主时钟信号; 从时钟信号被指定为主时钟信号的计算机同时并行地提供主时钟信号给网络中的所有其他计算机; 并且通过多路复用器和锁相环将网络中的每台计算机同时并行地并行地提供主网络中的所有计算机的主时钟信号，其中主时钟信号通过每个计算机上的锁相环锁定在所有计算机上电脑。

7. 发明授权

US5086387A Multi-frequency clock generation with low state coincidence upon latching 失效
标题翻译：闭锁时低状态重合的多频时钟产生
公开(公告)号：US5086387A
公开(公告)日：1992-02-04
申请号：US203586
申请日：1988-05-27
申请人： Ronald X. Arroyo , James T. Hanna
发明人： Ronald X. Arroyo , James T. Hanna
IPC分类号： G06F1/08
CPC分类号： G06F1/324 , G06F1/08 , Y02B60/1217
摘要： A clocking circuit connected to a processor for regulating processor operation and including a control circuit that produces a clock signal at a first frequency or for producing a clock signal at a designated one of a plurality of other selectable frequencies in response to a change signal from the processor. The control circuit is connected to a designating circuit that provides a signal to the control circuit to designate one of the selectable frequencies. In the preferred embodiment, the clocking circuit includes a register addressable by the processor and a frequency generator that generates several signals having unique frequencies. The processor may designate one of the frequencies as the clocking frequency by providing the appropriate data to the register. Upon the occurrence of an external event such as a DMA request or an interrupt, the control circuit will provide the clocking signal at a predetermined frequency.
摘要翻译：连接到处理器的时钟电路，用于调节处理器的操作，并包括一个控制电路，该控制电路产生一个第一频率的时钟信号，或响应于来自多个其它可选频率的改变信号产生一个指定的一个其他可选频率的时钟信号处理器。控制电路连接到指定电路，其向控制电路提供信号以指定可选频率之一。在优选实施例中，时钟电路包括可由处理器寻址的寄存器和产生具有唯一频率的多个信号的频率发生器。处理器可以通过向寄存器提供适当的数据来将频率中的一个指定为时钟频率。在外部事件（例如DMA请求或中断）发生时，控制电路将以预定频率提供时钟信号。

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