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1. 发明授权

US4791557A Apparatus and method for monitoring and controlling the prefetching of instructions by an information processing system 失效
标题翻译：用于监测和控制由信息处理系统预取指令的装置和方法
公开(公告)号：US4791557A
公开(公告)日：1988-12-13
申请号：US761213
申请日：1985-07-31
申请人： David J. Angel , Gary A. Cardone , Mark D. Holbrook , James P. Moskun , Bruce Patterson
发明人： David J. Angel , Gary A. Cardone , Mark D. Holbrook , James P. Moskun , Bruce Patterson
IPC分类号： G06F9/48 , G06F9/318 , G06F9/38 , G06F9/455 , G06F9/42
CPC分类号： G06F9/3017 , G06F9/3861
摘要： An information processing system includes a processor responsive to instructions for performing operations. The processor includes instruction queue for fetching and storing instructions in advance of execution and the system is responsive to certain of the instructions for causing execution of a corresponding sequence of instructions. A prefetch monitor includes circuitry for detecting instructions which may result in the execution of a corresponding sequence of instructions. The prefetch monitor further includes an instruction substitution circuit which is responsive to the detecting circuitry for inhibiting the reading of following instructions from a memory to the processor and is responsive to instruction fetching operation of the processor for reading null instructions to the processor. The prefetch monitor also includes a synchronization which is responsive to a fetching operation of the processor circuit for detecting transfer of execution to a next valid instruction, wherein the substitution circuit is responsive to the synchronization circuit for resuming reading of instructions from the memory to the processor with the next valid instruction. The synchronization includes circuitry for maintaining synchronization between the operations of substituting null instructions and the execution of the instructions. In a specific implementation, the instructions which may result in the execution of a corresponding sequence of instructions are foreign to the system, a corresponding non-maskable interrupt results in the execution of a routine which emulates the execution of the foreign instruction and the null instructions are jump-to-self instructions.
摘要翻译：信息处理系统包括响应于执行操作的指令的处理器。处理器包括用于在执行之前获取和存储指令的指令队列，并且系统响应于某些指令以引起执行相应的指令序列。预取监视器包括用于检测可能导致相应指令序列的执行的指令的电路。预取监视器还包括指令替换电路，其响应于检测电路，用于禁止从存储器向处理器读取后续指令，并响应于处理器的指令获取操作，以向处理器读取空指令。预取监视器还包括响应于用于检测执行到下一个有效指令的处理器电路的提取操作的同步，其中替代电路响应于同步电路，用于恢复从存储器到处理器的指令读取与下一个有效的指令。该同步包括用于维持替代空指令的操作与指令的执行之间的同步的电路。在具体实现中，可能导致相应指令序列的执行的指令对于系统是外来的，相应的不可屏蔽中断导致执行模拟外部指令和空指令的执行的例程是跳到自我的指示。

2. 发明授权

US4727480A Emulation of a data processing system 失效
标题翻译：数据处理系统的仿真
公开(公告)号：US4727480A
公开(公告)日：1988-02-23
申请号：US629028
申请日：1984-07-09
申请人： Loren O. Albright , David J. Angel , Patrick Klos , James P. Moskun , Carol W. Tyler
发明人： Loren O. Albright , David J. Angel , Patrick Klos , James P. Moskun , Carol W. Tyler
IPC分类号： G06F11/26 , G06F9/44 , G06F9/455 , G06F9/46 , G06F9/48 , G06F13/10 , G06F9/00
CPC分类号： G06F13/105
摘要： Emulation method and apparatus allowing a first system, which is not designed as a functional duplicate of a second system, to emulate the second system. The input/output structure of the second system is emulated in the first system by means of routines stored therein and which direct the already existing input/output structure to operate in the same manner as the input/output structure of the second system. The emulation routines are in turn invoked through the non-maskable interrupt mechanism of the first system by a modification thereto which detects the occurrence of "foreign" input/output requests; that is, input/output requests occuring in programs originally written for the second system and which are not normally recognized by the first system. The means for detecting foreign input/output requests includes means for comparing input/output request port addresses to the range of port addresses occupied by the system input/output devices and indicating when a port address is within the range of address space occupied by the system input/output devices. The foreign request detection means generates a non-maskable interrupt to invoke an input/output emulation routine upon the occurrence of input/output requests which do not normally fall within the range of input/output ports supported by the first system.
摘要翻译：允许不被设计为第二系统的功能副本的第一系统模拟第二系统的仿真方法和装置。第二系统的输入/输出结构通过存储在其中的程序在第一系统中被仿真，并且以与第二系统的输入/输出结构相同的方式指导已经存在的输入/输出结构来操作。通过其检测“外部”输入/输出请求的发生的修改，通过第一系统的不可屏蔽中断机制来调用仿真例程; 也就是说，最初为第二系统编写的程序中的输入/输出请求发生，而第一系统通常不被识别。用于检测外部输入/输出请求的装置包括用于将输入/输出请求端口地址与系统输入/输出设备占用的端口地址的范围进行比较并指示端口地址何时在系统占用的地址空间范围内的装置输入/输出设备。外部请求检测装置在出现通常不在第一系统支持的输入/输出端口范围内的输入/输出请求时产生不可屏蔽的中断来调用输入/输出仿真程序。

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