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1. 发明授权

US07930688B2 Scheduling technique for software pipelining 失效
公开(公告)号：US07930688B2
公开(公告)日：2011-04-19
申请号：US11969114
申请日：2008-01-03
申请人： Allen Russell Martin , James Lawrence McInnes
发明人： Allen Russell Martin , James Lawrence McInnes
IPC分类号： G06F9/45
CPC分类号： G06F8/4452 , G06F9/3838
摘要： An improved scheduling technique for software pipelining is disclosed which is designed to find schedules requiring fewer processor clock cycles and reduce register pressure hot spots when scheduling multiple groups of instructions (e.g. as represented by multiple sub-graphs of a DDG) which are independent, and substantially identical. The improvement in instruction scheduling and reduction of hot spots is achieved by evenly distributing such groups of instructions around the schedule for a given loop.

2. 发明授权

US07669194B2 Fine-grained software-directed data prefetching using integrated high-level and low-level code analysis optimizations 失效
标题翻译：使用集成的高级和低级代码分析优化进行细粒度的软件导向数据预取
公开(公告)号：US07669194B2
公开(公告)日：2010-02-23
申请号：US10926595
申请日：2004-08-26
申请人： Roch Georges Archambault , Robert James Blainey , Yaoqing Gao , Allan Russell Martin , James Lawrence McInnes , Francis Patrick O'Connell
发明人： Roch Georges Archambault , Robert James Blainey , Yaoqing Gao , Allan Russell Martin , James Lawrence McInnes , Francis Patrick O'Connell
IPC分类号： G06F9/44 , G06F9/45 , G06F9/30
CPC分类号： G06F8/4442
摘要： A mechanism for minimizing effective memory latency without unnecessary cost through fine-grained software-directed data prefetching using integrated high-level and low-level code analysis and optimizations is provided. The mechanism identifies and classifies streams, identifies data that is most likely to incur a cache miss, exploits effective hardware prefetching to determine the proper number of streams to be prefetched, exploits effective data prefetching on different types of streams in order to eliminate redundant prefetching and avoid cache pollution, and uses high-level transformations with integrated lower level cost analysis in the instruction scheduler to schedule prefetch instructions effectively.
摘要翻译：提供了一种通过使用集成高级和低级代码分析和优化的细粒度软件导向数据预取来最小化有效存储器延迟而不需要成本的机制。该机制识别和分类流，识别最可能引起缓存未命中的数据，利用有效的硬件预取来确定要预取的流的适当数量，利用不同类型的流上的有效数据预取，以消除冗余预取和避免高速缓存污染，并在指令调度程序中使用集成较低级别成本分析的高级转换，有效地调度预取指令。

3. 发明授权

US07506331B2 Method and apparatus for determining the profitability of expanding unpipelined instructions 失效
标题翻译：用于确定扩展无通知指令的盈利能力的方法和装置
公开(公告)号：US07506331B2
公开(公告)日：2009-03-17
申请号：US10930042
申请日：2004-08-30
申请人： Roch Georges Archambault , Robert Frederick Enenkel , Robert William Hay , Allan Russell Martin , James Lawrence McInnes , Ronald Ian McIntosh , Mark Peter Mendell
发明人： Roch Georges Archambault , Robert Frederick Enenkel , Robert William Hay , Allan Russell Martin , James Lawrence McInnes , Ronald Ian McIntosh , Mark Peter Mendell
IPC分类号： G06F9/45
CPC分类号： G06F8/443
摘要： A method, apparatus, and computer instructions for processing instructions. A data dependency graph is built. The data dependency graph is analyzed for recurrences, and unpipelined instructions that lie outside of the recurrences are expanded.
摘要翻译：一种用于处理指令的方法，装置和计算机指令。构建数据依赖图。分析数据依赖关系图以进行复现，扩展位于复发之外的无关注指令。

4. 发明授权

US07478379B2 Method for minimizing spill in code scheduled by a list scheduler 失效
标题翻译：用于最小化由列表调度程序调度的代码中的溢出的方法
公开(公告)号：US07478379B2
公开(公告)日：2009-01-13
申请号：US10840088
申请日：2004-05-06
申请人： Damien Bonaventure , James Lawrence McInnes
发明人： Damien Bonaventure , James Lawrence McInnes
IPC分类号： G06F9/44 , G06F9/48 , G06F9/40
CPC分类号： G06F8/445
摘要： A technique of ordering machine instructions to reduce spill code. For each machine instruction that is ready for scheduling, an amount is determined by which the size of a committed set of machine instructions would increase upon the scheduling of the machine instruction. The machine instruction for which the determined amount is smallest is then scheduled. The currently committed instructions may be determined to be the machine instructions that are already scheduled as well as the machine instructions that are descendent from already scheduled machine instructions. The result is that new computations upon which a target processor will embark tend to be deferred. Bit vectors may be employed for efficiency during the assessment of candidate instructions that are ready for scheduling. The technique may be triggered when the risk of registers becoming overcommitted becomes high, as may occur when the number of available processor registers drops below a certain threshold.
摘要翻译：订购机器指令以减少溢出代码的技术。对于准备进行调度的每个机器指令，根据机器指令的调度，确定机器指令的一定程度的大小将被确定。然后调度确定量最小的机器指令。可以将当前承诺的指令确定为已经被调度的机器指令以及从已经调度的机器指令后代的机器指令。结果是，目标处理器将趋于延迟的新计算。可以在准备好进行调度的候选指令的评估期间采用位向量的效率。当寄存器过度承担的风险变高时，可能会触发该技术，如可用处理器寄存器的数量低于某个阈值时可能会发生的。

5. 发明授权

US5787284A Improving memory layout based on connectivity considerations 失效
标题翻译：基于连接性考虑改进内存布局
公开(公告)号：US5787284A
公开(公告)日：1998-07-28
申请号：US726038
申请日：1996-10-07
申请人： Robert James Blainey , Christopher Michael Donawa , James Lawrence McInnes
发明人： Robert James Blainey , Christopher Michael Donawa , James Lawrence McInnes
IPC分类号： G06F9/45
CPC分类号： G06F8/443 , G06F9/44557
摘要： A technique used during interprocedural compilation in which program objects are grouped together based on the weights of the connections between the objects and their costs. System-imposed constraints on memory size can be taken into account to avoid creating groupings that overload the system's capacity. The groupings can be distributed over memories located on different processors.
摘要翻译：在过程间编译期间使用的技术，其中程序对象基于对象与其成本之间的连接的权重而分组在一起。可以考虑系统对内存大小的限制，以避免创建使系统容量过大的分组。分组可以分布在位于不同处理器上的存储器上。

6. 发明授权

US07962907B2 Scheduling technique for software pipelining 失效
标题翻译：软件流水线调度技术
公开(公告)号：US07962907B2
公开(公告)日：2011-06-14
申请号：US11840371
申请日：2007-08-17
申请人： Allan Russell Martin , James Lawrence McInnes
发明人： Allan Russell Martin , James Lawrence McInnes
IPC分类号： G06F9/44
CPC分类号： G06F8/4452 , G06F9/3838
摘要： An improved scheduling technique for software pipelining is disclosed which is designed to find schedules requiring fewer processor clock cycles and reduce register pressure hot spots when scheduling multiple groups of instructions (e.g. as represented by multiple sub-graphs of a DDG) which are independent, and substantially identical. The improvement in instruction scheduling and reduction of hot spots is achieved by evenly distributing such groups of instructions around the schedule for a given loop.
摘要翻译：公开了一种用于软件流水线的改进的调度技术，其被设计为在调度多个独立的指令组（例如，由DDG的多个子图表示）时，需要更少的处理器时钟周期并减少寄存器压力热点，以及基本相同。指令调度的改善和热点的减少是通过围绕给定循环的时间表均匀分布这些指令组来实现的。

7. 发明申请

US20100095271A1 Fine-Grained Software-Directed Data Prefetching Using Integrated High-Level and Low-Level Code Analysis Optimizations 有权
标题翻译：使用集成的高级和低级代码分析优化进行细粒度软件定向数据预取
公开(公告)号：US20100095271A1
公开(公告)日：2010-04-15
申请号：US12644756
申请日：2009-12-22
申请人： Roch Georges Archambault , Robert James Blainey , Yaoqing Gao , Allan Russell Martin , James Lawrence McInnes , Francis Patrick O'Connell
发明人： Roch Georges Archambault , Robert James Blainey , Yaoqing Gao , Allan Russell Martin , James Lawrence McInnes , Francis Patrick O'Connell
IPC分类号： G06F9/44
CPC分类号： G06F8/4442
摘要： A mechanism for minimizing effective memory latency without unnecessary cost through fine-grained software-directed data prefetching using integrated high-level and low-level code analysis and optimizations is provided. The mechanism identifies and classifies streams, identifies data that is most likely to incur a cache miss, exploits effective hardware prefetching to determine the proper number of streams to be prefetched, exploits effective data prefetching on different types of streams in order to eliminate redundant prefetching and avoid cache pollution, and uses high-level transformations with integrated lower level cost analysis in the instruction scheduler to schedule prefetch instructions effectively.
摘要翻译：提供了一种通过使用集成高级和低级代码分析和优化的细粒度软件导向数据预取来最小化有效存储器延迟而不需要成本的机制。该机制识别和分类流，识别最可能引起缓存未命中的数据，利用有效的硬件预取来确定要预取的流的适当数量，利用不同类型的流上的有效数据预取，以消除冗余预取和避免高速缓存污染，并在指令调度程序中使用集成较低级别成本分析的高级转换，有效地调度预取指令。

8. 发明授权

US07331045B2 Scheduling technique for software pipelining 失效
标题翻译：软件流水线调度技术
公开(公告)号：US07331045B2
公开(公告)日：2008-02-12
申请号：US10835129
申请日：2004-04-29
申请人： Allan Russell Martin , James Lawrence McInnes
发明人： Allan Russell Martin , James Lawrence McInnes
IPC分类号： G06F9/45
CPC分类号： G06F8/4452 , G06F9/3838
摘要： An improved scheduling technique for software pipelining is disclosed which is designed to find schedules requiring fewer processor clock cycles and reduce register pressure hot spots when scheduling multiple groups of instructions (e.g. as represented by multiple sub-graphs of a DDG) which are independent, and substantially identical. The improvement in instruction scheduling and reduction of hot spots is achieved by evenly distributing such groups of instructions around the schedule for a given loop.
摘要翻译：公开了一种用于软件流水线的改进的调度技术，其被设计为在调度多个独立的指令组（例如，由DDG的多个子图表示）时，需要更少的处理器时钟周期并减少寄存器压力热点，以及基本相同。指令调度的改善和热点的减少是通过围绕给定循环的时间表均匀分布这些指令组来实现的。

9. 发明授权

US5850549A Global variable coalescing 失效
标题翻译：全局变量合并
公开(公告)号：US5850549A
公开(公告)日：1998-12-15
申请号：US726039
申请日：1996-10-07
申请人： Robert James Blainey , Christopher Michael Donawa , James Lawrence McInnes
发明人： Robert James Blainey , Christopher Michael Donawa , James Lawrence McInnes
IPC分类号： G06F9/45
CPC分类号： G06F8/443 , G06F8/433
摘要： An interprocedural compilation method for aggregating global data variables in external storage to maximize data locality. Using the information displayed in a weighted interference graph in which node weights represent the size of data stored in each global variable and edges between variables represent access relationships between the globals, the global variables can be mapped into aggregates based on this frequency of access, while preventing the cumulative data size in any aggregate from exceeding a memory size restriction.
摘要翻译：用于聚合外部存储中的全局数据变量的过程间编译方法，以最大限度地提高数据的局部性。使用显示在加权干涉图中的信息，其中节点权重表示存储在每个全局变量中的数据的大小和变量之间的边界表示全局变量之间的访问关系，全局变量可以基于该访问频率被映射到聚合中，而防止任何聚合中的累积数据大小超过内存大小限制。

10. 发明授权

US5797012A Connectivity based program partitioning 失效
标题翻译：基于连接的程序分区
公开(公告)号：US5797012A
公开(公告)日：1998-08-18
申请号：US727720
申请日：1996-10-07
申请人： Robert James Blainey , Christopher Michael Donawa , James Lawrence McInnes
发明人： Robert James Blainey , Christopher Michael Donawa , James Lawrence McInnes
IPC分类号： G06F9/45
CPC分类号： G06F8/443
摘要： A method for partitioning programs into multi-procedure modules for efficient compilation. During interprocedural analysis, a weighted callgraph of the program is constructed in which weights on nodes represent code size of each procedure and weights on edges between the nodes represent execution counts between procedures. A coloured interference graph is built from the analysis information, and is used to induce weighted sub-graphs of the callgraph containing no interferences between procedures in each sub-graph. The procedures from a single sub-graph are combined into one or more modules; procedures with the highest weighted edges between them are combined in a module first until the cumulative node weight of the module reaches a preset limit on memory size.
摘要翻译：一种将程序划分为多程序模块以实现高效编译的方法。在过程间分析期间，构建了程序的加权调用，其中节点上的权重表示每个过程的代码大小，并且节点之间的边上的权重表示过程之间的执行计数。彩色干涉图是从分析信息构建的，用于诱导不包含每个子图中的过程之间干扰的呼叫图的加权子图。来自单个子图的过程被组合成一个或多个模块; 在它们之间具有最高加权边缘的程序首先被组合在模块中，直到模块的累积节点权重达到存储器大小的预设限制。

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