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1. 发明授权

US09847266B2 Method of fabricating semiconductor device 有权
公开(公告)号：US09847266B2
公开(公告)日：2017-12-19
申请号：US15165684
申请日：2016-05-26
申请人： Tae-Hwa Kim , Chanhoon Park , Dongsoo Lee , Jaehyun Lee , Hyung Joo Lee , Kangmin Jeon , Kyounghoon Han
发明人： Tae-Hwa Kim , Chanhoon Park , Dongsoo Lee , Jaehyun Lee , Hyung Joo Lee , Kangmin Jeon , Kyounghoon Han
IPC分类号： H01L21/00 , H01L21/66 , H01L27/11582 , H01L21/28 , H01L21/3213 , H01L21/311 , H01J37/32 , H01L27/11556
CPC分类号： H01L22/26 , H01J37/32963 , H01J2237/334 , H01L21/28008 , H01L21/31116 , H01L21/32135 , H01L22/12 , H01L27/11556 , H01L27/11582
摘要： A method of fabricating a semiconductor device includes etching a stack of first-material layers and second-material layers alternately disposed one on another on a substrate. An upper portion of the stack is etched using an end point detection (EPD) signal of an etching reaction gas, and a function of an injection time of an etchant with respect to a depth of an opening is obtained while the upper portion of the stack is etched. A lower portion of the stack is etched using the obtained function.

2. 发明申请

US20160379903A1 METHOD OF FABRICATING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20160379903A1
公开(公告)日：2016-12-29
申请号：US15165684
申请日：2016-05-26
申请人： TAE-HWA KIM , CHANHOON PARK , DONGSOO LEE , JAEHYUN LEE , HYUNG JOO LEE , KANGMIN JEON , KYOUNGHOON HAN
发明人： TAE-HWA KIM , CHANHOON PARK , DONGSOO LEE , JAEHYUN LEE , HYUNG JOO LEE , KANGMIN JEON , KYOUNGHOON HAN
IPC分类号： H01L21/66 , H01L21/311 , H01L21/3213 , H01L27/115 , H01L21/28
CPC分类号： H01L22/26 , H01J37/32963 , H01J2237/334 , H01L21/28008 , H01L21/31116 , H01L21/32135 , H01L22/12 , H01L27/11556 , H01L27/11582
摘要： A method of fabricating a semiconductor device includes etching a stack of first-material layers and second-material layers alternately disposed one on another on a substrate. An upper portion of the stack is etched using an end point detection (EPD) signal of an etching reaction gas, and a function of an injection time of an etchant with respect to a depth of an opening is obtained while the upper portion of the stack is etched. A lower portion of the stack is etched using the obtained function.
摘要翻译：一种制造半导体器件的方法包括：在衬底上相互交替布置的第一材料层和第二材料层的叠层的蚀刻。使用蚀刻反应气体的端点检测（EPD）信号来蚀刻堆叠的上部，并且获得蚀刻剂相对于开口深度的喷射时间的功能，同时堆叠的上部被蚀刻。使用所获得的功能蚀刻堆叠的下部。

3. 发明授权

US08524538B2 Integrated circuit packaging system with film assistance mold and method of manufacture thereof 有权
标题翻译：具有胶片辅助模具的集成电路封装系统及其制造方法
公开(公告)号：US08524538B2
公开(公告)日：2013-09-03
申请号：US13327091
申请日：2011-12-15
申请人： JaeHyun Lee , Ki Youn Jang , DokOk Yu
发明人： JaeHyun Lee , Ki Youn Jang , DokOk Yu
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L21/00
CPC分类号： H01L23/3121 , H01L21/566 , H01L24/16 , H01L2224/16225 , H01L2924/18161
摘要： A method of manufacture of an integrated circuit packaging system includes: providing a substrate; mounting an integrated circuit over the substrate, the integrated circuit having an inactive side and a non-horizontal side; mounting a mold chase having a buffer layer over the integrated circuit; forming an encapsulation between the substrate and the buffer; and removing the mold chase, leaving the encapsulation having a recess exposing a portion of the non-horizontal side.
摘要翻译：一种集成电路封装系统的制造方法，包括：提供基板; 在衬底上安装集成电路，集成电路具有非活动侧和非水平侧; 在所述集成电路上安装具有缓冲层的模具追逐; 在衬底和缓冲器之间形成封装; 并且移除模具追逐，留下具有暴露非水平侧部分的凹部的封装。

4. 发明申请

US20110279789A1 PROJECTION DISPLAY DEVICE 有权
标题翻译：投影显示设备
公开(公告)号：US20110279789A1
公开(公告)日：2011-11-17
申请号：US13104382
申请日：2011-05-10
申请人： Hiromitsu Gishi , Taichi Yoshimura , Kouji Shiraito , Jaehyun Lee
发明人： Hiromitsu Gishi , Taichi Yoshimura , Kouji Shiraito , Jaehyun Lee
IPC分类号： G03B21/16
CPC分类号： G03B21/16 , H04N9/3144
摘要： A projection display device is provided with a main body cabinet; a projection port which is formed in the main body cabinet to guide modulated light to an outside of the projection display device; an air outlet which is formed at least in one of two surfaces of the main body cabinet facing each other across the projection port; and an exhaust unit which discharges, to the outside, air that has been warmed by heat exchange with a member to be cooled which is disposed in the main body cabinet through the air outlet. In this arrangement, the exhaust unit includes an exhaust fan, and a deflection member which deflects air discharged from the exhaust fan in a direction away from the projection plane.
摘要翻译：投影显示装置设有主体机壳; 突出端口，其形成在主体机壳中以将调制的光引导到投影显示装置的外部; 空气出口，其形成在所述主体机壳的至少两个表面中的至少一个中，所述空气出口相对于所述突出端口彼此面对; 以及排气单元，其通过空气出口将与被冷却部件进行热交换而被加温的空气排出到主体机壳内。在这种布置中，排气单元包括排气扇和偏转构件，该偏转构件沿着远离投影平面的方向偏转从排气扇排出的空气。

5. 发明授权

US10096540B2 Semiconductor device and method of forming dummy pillars between semiconductor die and substrate for maintaining standoff distance 有权
公开(公告)号：US10096540B2
公开(公告)日：2018-10-09
申请号：US13107075
申请日：2011-05-13
申请人： KyungHoon Lee , SeongWon Park , KiYoun Jang , JaeHyun Lee
发明人： KyungHoon Lee , SeongWon Park , KiYoun Jang , JaeHyun Lee
IPC分类号： H01L23/498 , H01L21/50 , H01L21/56 , H01L23/31 , H01L23/00
摘要： A semiconductor device has a semiconductor die with an insulation layer formed over an active surface of the semiconductor die. A conductive layer is formed over the first insulating layer electrically connected to the active surface. A plurality of conductive pillars is formed over the conductive layer. A plurality of dummy pillars is formed over the first insulating layer electrically isolated from the conductive layer and conductive pillars. The semiconductor die is mounted to a substrate. A height of the dummy pillars is greater than a height of the conductive pillars to maintain the standoff distance between the semiconductor die and substrate. The dummy pillars can be formed over the substrate. The dummy pillars are disposed at corners of the semiconductor die and a central region of the semiconductor die. A mold underfill material is deposited between the semiconductor die and substrate.

6. 发明授权

US09158186B2 Projection display device 有权
标题翻译：投影显示设备
公开(公告)号：US09158186B2
公开(公告)日：2015-10-13
申请号：US13104382
申请日：2011-05-10
申请人： Hiromitsu Gishi , Taichi Yoshimura , Kouji Shiraito , Jaehyun Lee
发明人： Hiromitsu Gishi , Taichi Yoshimura , Kouji Shiraito , Jaehyun Lee
IPC分类号： G03B21/18 , G03B21/16 , H04N9/31
CPC分类号： G03B21/16 , H04N9/3144
摘要： A projection display device is provided with a main body cabinet; a projection port which is formed in the main body cabinet to guide modulated light to an outside of the projection display device; an air outlet which is formed at least in one of two surfaces of the main body cabinet facing each other across the projection port; and an exhaust unit which discharges, to the outside, air that has been warmed by heat exchange with a member to be cooled which is disposed in the main body cabinet through the air outlet. In this arrangement, the exhaust unit includes an exhaust fan, and a deflection member which deflects air discharged from the exhaust fan in a direction away from the projection plane.
摘要翻译：投影显示装置设有主体机壳; 突出端口，其形成在主体机壳中以将调制的光引导到投影显示装置的外部; 空气出口，其形成在所述主体机壳的至少两个表面中的至少一个中，所述空气出口相对于所述突出端口彼此面对; 以及排气单元，其通过空气出口将与被冷却部件进行热交换而被加温的空气排出到主体机壳内。在这种布置中，排气单元包括排气扇和偏转构件，该偏转构件沿着远离投影平面的方向偏转从排气扇排出的空气。

7. 发明申请

US20130154121A1 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FILM ASSISTANCE MOLD AND METHOD OF MANUFACTURE THEREOF 有权
标题翻译：具有薄膜辅助模具的集成电路包装系统及其制造方法
公开(公告)号：US20130154121A1
公开(公告)日：2013-06-20
申请号：US13327091
申请日：2011-12-15
申请人： JaeHyun Lee , Ki Youn Jang , DokOk Yu
发明人： JaeHyun Lee , Ki Youn Jang , DokOk Yu
IPC分类号： H01L23/28 , H01L21/56
CPC分类号： H01L23/3121 , H01L21/566 , H01L24/16 , H01L2224/16225 , H01L2924/18161
摘要： A method of manufacture of an integrated circuit packaging system includes: providing a substrate; mounting an integrated circuit over the substrate, the integrated circuit having an inactive side and a non-horizontal side; mounting a mold chase having a buffer layer over the integrated circuit; forming an encapsulation between the substrate and the buffer; and removing the mold chase, leaving the encapsulation having a recess exposing a portion of the non-horizontal side.
摘要翻译：一种集成电路封装系统的制造方法，包括：提供基板; 在衬底上安装集成电路，集成电路具有非活动侧和非水平侧; 在所述集成电路上安装具有缓冲层的模具追逐; 在衬底和缓冲器之间形成封装; 并且移除模具追逐，留下具有暴露非水平侧部分的凹部的封装。

8. 发明申请

US20130069221A1 Semiconductor Device and Method of Forming Conductive Protrusions Over Conductive Pillars or Bond Pads as Fixed Offset Vertical Interconnect Structures 有权
标题翻译：半导体器件和导电突起形成导电支柱或粘结垫作为固定偏移垂直互连结构
公开(公告)号：US20130069221A1
公开(公告)日：2013-03-21
申请号：US13234366
申请日：2011-09-16
申请人： JaeHyun Lee , KyungHoon Lee , SeongWon Park , KiYoun Jang
发明人： JaeHyun Lee , KyungHoon Lee , SeongWon Park , KiYoun Jang
IPC分类号： H01L23/498 , H01L21/56
CPC分类号： H01L24/13 , H01L23/3114 , H01L23/3128 , H01L23/49811 , H01L24/16 , H01L24/81 , H01L2224/0401 , H01L2224/05111 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05164 , H01L2224/05166 , H01L2224/05169 , H01L2224/05171 , H01L2224/05186 , H01L2224/05611 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/1132 , H01L2224/11334 , H01L2224/1145 , H01L2224/1146 , H01L2224/11472 , H01L2224/11474 , H01L2224/11903 , H01L2224/13076 , H01L2224/13082 , H01L2224/131 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13124 , H01L2224/13139 , H01L2224/13147 , H01L2224/13155 , H01L2224/13166 , H01L2224/13184 , H01L2224/16238 , H01L2224/2919 , H01L2224/32225 , H01L2224/73204 , H01L2224/73265 , H01L2224/81191 , H01L2224/81193 , H01L2224/81815 , H01L2224/83104 , H01L2224/94 , H01L2924/01322 , H01L2924/12041 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/15311 , H01L2924/181 , H01L2924/3841 , H01L2924/00 , H01L2224/11 , H01L2224/03 , H01L2924/00014 , H01L2924/00012 , H01L2924/014 , H01L2924/01082 , H01L2924/01074 , H01L2924/04941 , H01L2924/01023 , H01L2924/01029 , H01L2924/0665
摘要： A semiconductor device has a semiconductor die mounted to a substrate. A plurality of conductive pillars is formed over a semiconductor die. A plurality of conductive protrusions is formed over the conductive pillars. Bumps are formed over the conductive protrusions and conductive pillars. Alternatively, the conductive protrusions are formed over the substrate. A conductive layer is formed over the substrate. The semiconductor die is mounted to the substrate by reflowing the bumps at a temperature that is less than a melting point of the conductive pillars and conductive protrusions to metallurgically and electrically connect the bumps to the conductive layer while maintaining a fixed offset between the semiconductor die and substrate. The fixed offset between the semiconductor die and substrate is determined by a height of the conductive pillars and a height of the conductive protrusions. A mold underfill material is deposited between the semiconductor die and substrate.
摘要翻译：半导体器件具有安装到衬底的半导体管芯。在半导体管芯上形成多个导电柱。多个导电突起形成在导电柱上。凸起形成在导电突起和导电柱上。或者，导电突起形成在衬底上。导电层形成在衬底上。半导体管芯通过在小于导电柱和导电突起的熔点的温度下回流焊接而安装到衬底上，以将凸点冶金和电连接到导电层，同时保持半导体管芯和半导体管芯之间的固定偏移基质。半导体管芯和衬底之间的固定偏移由导电柱的高度和导电突起的高度决定。模具底部填充材料沉积在半导体管芯和衬底之间。

9. 发明申请

US20120286418A1 Semiconductor Device and Method of Forming Dummy Pillars Between Semiconductor Die and Substrate for Maintaining Standoff Distance 审中-公开
标题翻译：半导体器件和在半导体管芯和衬底之间形成虚拟柱的方法，用于维持间隔距离
公开(公告)号：US20120286418A1
公开(公告)日：2012-11-15
申请号：US13107075
申请日：2011-05-13
申请人： KyungHoon Lee , SeongWon Park , KiYoun Jang , JaeHyun Lee
发明人： KyungHoon Lee , SeongWon Park , KiYoun Jang , JaeHyun Lee
IPC分类号： H01L23/498 , H01L21/50
CPC分类号： H01L23/49811 , H01L21/563 , H01L23/3121 , H01L23/3128 , H01L23/3192 , H01L24/02 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/81 , H01L24/94 , H01L2224/0231 , H01L2224/0239 , H01L2224/03013 , H01L2224/0332 , H01L2224/0343 , H01L2224/0345 , H01L2224/03452 , H01L2224/03462 , H01L2224/03464 , H01L2224/0347 , H01L2224/0361 , H01L2224/03912 , H01L2224/0401 , H01L2224/05548 , H01L2224/05611 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/05671 , H01L2224/10135 , H01L2224/10165 , H01L2224/1132 , H01L2224/11334 , H01L2224/1145 , H01L2224/11452 , H01L2224/11462 , H01L2224/11464 , H01L2224/11849 , H01L2224/11901 , H01L2224/13082 , H01L2224/131 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/16145 , H01L2224/16146 , H01L2224/2929 , H01L2224/48091 , H01L2224/73204 , H01L2224/73265 , H01L2224/81007 , H01L2224/81139 , H01L2224/8114 , H01L2224/81815 , H01L2224/83104 , H01L2224/94 , H01L2924/01029 , H01L2924/01322 , H01L2924/12041 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/181 , H01L2924/381 , H01L2924/3841 , H01L2924/00014 , H01L2924/01074 , H01L2924/014 , H01L2924/01082 , H01L2924/01013 , H01L2924/0105 , H01L2924/01028 , H01L2924/01079 , H01L2924/01047 , H01L2224/11 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor device has a semiconductor die with an insulation layer formed over an active surface of the semiconductor die. A conductive layer is formed over the first insulating layer electrically connected to the active surface. A plurality of conductive pillars is formed over the conductive layer. A plurality of dummy pillars is formed over the first insulating layer electrically isolated from the conductive layer and conductive pillars. The semiconductor die is mounted to a substrate. A height of the dummy pillars is greater than a height of the conductive pillars to maintain the standoff distance between the semiconductor die and substrate. The dummy pillars can be formed over the substrate. The dummy pillars are disposed at corners of the semiconductor die and a central region of the semiconductor die. A mold underfill material is deposited between the semiconductor die and substrate.
摘要翻译：半导体器件具有形成在半导体管芯的有效表面上的绝缘层的半导体管芯。导电层形成在与主动表面电连接的第一绝缘层上。多个导电柱形成在导电层上。在与导电层和导电柱电隔离的第一绝缘层上形成多个虚拟柱。将半导体管芯安装到基板上。虚拟柱的高度大于导电柱的高度，以保持半导体管芯和衬底之间的间隔距离。虚拟柱可以形成在衬底上。虚拟柱设置在半导体管芯的角部和半导体管芯的中心区域。模具底部填充材料沉积在半导体管芯和衬底之间。

10. 发明申请

US20120119360A1 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CONNECTION STRUCTURE AND METHOD OF MANUFACTURE THEREOF 有权
标题翻译：具有连接结构的集成电路包装系统及其制造方法
公开(公告)号：US20120119360A1
公开(公告)日：2012-05-17
申请号：US13298267
申请日：2011-11-16
申请人： YoungChul Kim , KyungHoon Lee , Seong Won Park , Ki Youn Jang , JaeHyun Lee , DeokKyung Yang , In Sang Yoon , SungEun Park
发明人： YoungChul Kim , KyungHoon Lee , Seong Won Park , Ki Youn Jang , JaeHyun Lee , DeokKyung Yang , In Sang Yoon , SungEun Park
IPC分类号： H01L23/498 , H01L21/50
CPC分类号： H01L21/565 , H01L23/3128 , H01L23/49811 , H01L23/49816 , H01L23/49822 , H01L24/16 , H01L24/48 , H01L25/105 , H01L2224/16225 , H01L2224/32225 , H01L2224/48227 , H01L2224/73204 , H01L2224/83102 , H01L2224/92125 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/01079 , H01L2924/14 , H01L2924/15311 , H01L2924/1533 , H01L2924/15331 , H01L2924/1815 , H01L2924/18161 , H01L2924/18165 , H01L2924/3511 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A method of manufacture of an integrated circuit packaging system includes: providing a substrate; attaching a connection post to the substrate, the connection post having a post top and a post side; mounting an integrated circuit die on the substrate, the integrated circuit die having a top die surface; and forming a package body on the substrate, the connection post, and the integrated circuit die.
摘要翻译：一种集成电路封装系统的制造方法，包括：提供基板; 将连接柱附接到所述基板，所述连接柱具有柱顶和柱侧; 在基板上安装集成电路管芯，集成电路管芯具有顶部管芯表面; 以及在所述基板，所述连接柱和所述集成电路管芯上形成封装体。

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