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1. 发明申请

US20170294443A1 VERTICAL MEMORY DEVICES HAVING DUMMY CHANNEL REGIONS 审中-公开
公开(公告)号：US20170294443A1
公开(公告)日：2017-10-12
申请号：US15626395
申请日：2017-06-19
申请人： JONG WON KIM , SEUNG HYUN LIM , CHANG SEOK KANG , YOUNG WOO PARK , DAE HOON BAE , DONG SEOG EUN , WOO SUNG LEE , JAE DUK LEE , JAE WOO LIM , HANMEI CHOI
发明人： JONG WON KIM , SEUNG HYUN LIM , CHANG SEOK KANG , YOUNG WOO PARK , DAE HOON BAE , DONG SEOG EUN , WOO SUNG LEE , JAE DUK LEE , JAE WOO LIM , HANMEI CHOI
IPC分类号： H01L27/11565 , H01L27/11524 , H01L27/11556 , H01L29/04 , H01L27/1157 , H01L27/11582 , H01L27/11573 , H01L27/11519 , H01L27/11529
CPC分类号： H01L27/11565 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11529 , H01L27/11556 , H01L27/11568 , H01L27/1157 , H01L27/11573 , H01L27/11582 , H01L28/00 , H01L29/04
摘要： A memory device includes a plurality of channel regions that each extend in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate adjacent the channel regions, each of the gate electrodes extending different lengths, and a plurality of dummy channel regions adjacent first ends of the plurality of gate electrode layers, wherein the substrate includes a substrate insulating layer formed below the plurality of dummy channel regions.

2. 发明申请

US20170040337A1 VERTICAL MEMORY DEVICES HAVING DUMMY CHANNEL REGIONS 有权
标题翻译：具有双向通道区域的垂直存储器件
公开(公告)号：US20170040337A1
公开(公告)日：2017-02-09
申请号：US14987835
申请日：2016-01-05
申请人： Jong Won KIM , Seung Hyun LIM , Chang Seok KANG , Young Woo PARK , Dae Hoon BAE , Dong Seog EUN , Woo Sung LEE , Jae Duk LEE , Jae Woo LIM , HanMei CHOI
发明人： Jong Won KIM , Seung Hyun LIM , Chang Seok KANG , Young Woo PARK , Dae Hoon BAE , Dong Seog EUN , Woo Sung LEE , Jae Duk LEE , Jae Woo LIM , HanMei CHOI
IPC分类号： H01L27/115
CPC分类号： H01L27/11565 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11529 , H01L27/11556 , H01L27/11568 , H01L27/1157 , H01L27/11573 , H01L27/11582 , H01L28/00 , H01L29/04
摘要： A memory device includes a plurality of channel regions that each extend in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate adjacent the channel regions, each of the gate electrodes extending different lengths, and a plurality of dummy channel regions adjacent first ends of the plurality of gate electrode layers, wherein the substrate includes a substrate insulating layer formed below the plurality of dummy channel regions.
摘要翻译：存储器件包括多个通道区域，每个沟道区域在垂直于衬底的上表面的方向上延伸，多个栅极电极层和堆叠在衬底上的与沟道区相邻的多个绝缘层，每个栅电极延伸不同长度，以及与多个栅电极层的第一端相邻的多个虚设通道区域，其中所述衬底包括形成在所述多个虚拟通道区域下方的衬底绝缘层。

3. 发明授权

US09564519B2 Non-volatile memory devices and manufacturing methods thereof 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US09564519B2
公开(公告)日：2017-02-07
申请号：US14457220
申请日：2014-08-12
申请人： Jin Taek Park , Young Woo Park , Jae Duk Lee
发明人： Jin Taek Park , Young Woo Park , Jae Duk Lee
IPC分类号： H01L29/66 , H01L29/778 , H01L29/792 , H01L27/115 , G11C16/04
CPC分类号： H01L29/513 , G11C16/0483 , H01L21/28273 , H01L27/11556 , H01L27/11582 , H01L29/42324 , H01L29/4234 , H01L29/42364 , H01L29/4916 , H01L29/66825 , H01L29/66833 , H01L29/7789 , H01L29/7926
摘要： There is provided a method of manufacturing a non-volatile memory device including: alternatively stacking a plurality of insulating layers and a plurality of conductive layers on a top surface of a substrate; forming an opening that exposes the top surface of the substrate and lateral surfaces of the insulating layers and the conductive layers; forming an anti-oxidation layer on at least the exposed lateral surfaces of the conductive layers; forming a gate dielectric layer on the anti-oxidation layer, the gate dielectric layer including a blocking layer, an electric charge storage layer, and a tunneling layer that are sequentially formed on the anti-oxidation layer; and forming a channel region on the tunneling layer.
摘要翻译：提供了一种制造非易失性存储器件的方法，包括：在衬底的顶表面上交替堆叠多个绝缘层和多个导电层; 形成露出所述基板的顶表面和所述绝缘层和所述导电层的侧表面的开口; 在所述导电层的至少暴露的侧表面上形成抗氧化层; 在所述抗氧化层上形成栅介电层，所述栅极介电层包括依次形成在所述抗氧化层上的阻挡层，电荷存储层和隧穿层; 以及在隧道层上形成沟道区。

4. 发明授权

US08248853B2 Methods of programming non-volatile flash memory devices by applying a higher voltage level to a selected word line than to a word line neighboring the selected word line 有权
标题翻译：通过对所选择的字线施加比毗邻所选字线的字线更高的电压电平来对非易失性闪存器件进行编程的方法
公开(公告)号：US08248853B2
公开(公告)日：2012-08-21
申请号：US12590701
申请日：2009-11-12
申请人： Jae Duk Lee , Soon Moon Jung , Jung Dal Choi
发明人： Jae Duk Lee , Soon Moon Jung , Jung Dal Choi
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/3418 , G11C16/3427
摘要： In a method of programming a non-volatile memory device, a first voltage is applied to a selected word line corresponding to a selected memory cell transistor of a selected transistor string to be programmed; a second voltage is applied to a neighboring word line neighboring the selected word line and corresponding to a neighboring transistor of the selected transistor string, wherein the first voltage is greater than the second voltage, the application of the first and second voltages to the selected and neighboring word lines respectively causing electrons to be generated by an electric field formed between the neighboring transistor and the selected memory cell transistor, the electrons accelerating toward the selected memory cell transistor and injecting into a charge storage layer of the selected memory cell transistor; wherein the neighboring transistor is positioned between the selected memory cell transistor and one of a ground select transistor and a string select transistor, and the first voltage is applied to unselected word lines corresponding to unselected memory cell transistors of the selected transistor string positioned between the selected memory cell transistor and the other of the ground select transistor and the string select transistor.
摘要翻译：在编程非易失性存储器件的方法中，将第一电压施加到对应于要编程的所选择的晶体管串的选定存储单元晶体管的选定字线; 第二电压被施加到与所选择的字线相邻并且对应于所选择的晶体管串的相邻晶体管的相邻字线，其中第一电压大于第二电压，将第一和第二电压施加到所选择的和分别使相邻的晶体管与所选择的存储单元晶体管之间形成的电场产生电子的相邻字线，电子向所选择的存储单元晶体管加速并注入到所选存储单元晶体管的电荷存储层中; 其中所述相邻晶体管位于所选择的存储单元晶体管和接地选择晶体管和串选择晶体管中的一个之间，并且所述第一电压被施加到对应于所选择的晶体管串的未选择存储单元晶体管的未选择字线，存储单元晶体管和另一个接地选择晶体管和串选择晶体管。

5. 发明申请

US20110268501A1 MANHOLE COVER 失效
标题翻译：男子封面
公开(公告)号：US20110268501A1
公开(公告)日：2011-11-03
申请号：US13143085
申请日：2009-12-29
申请人： Jae Duk Lee
发明人： Jae Duk Lee
IPC分类号： E02D29/14
CPC分类号： E02D29/14
摘要： The present invention relates to a manhole cover which has an upper body and a lower body coupled to each other to maintain balance, to endure loads applied from an external source in a stable manner, to protect the inside of the manhole from the ingress of rainwater, and to enable the upper body to be stably fixed inside the lower body. To accomplish the above-described aim, the key technical features of the present invention relate to a manhole cover, comprising: a lower body, the inside of which is hollow, with a spiral rib formed along the inner surface of the hollow space, and a convex-concave portion formed on the upper surface of the spiral rib; an upper body which is coupled inside the lower body, and the inside of which is hollow, with a spiral rib and a convex-concave portion formed along the outer surface thereof to correspond to the spiral rib and the convex-concave portion of the lower body, and a stepped portion formed at the upper surface thereof; a cover mounted in the stepped portion of the upper body to protect the inside of the upper body from the introduction of foreign objects; and a waterproofing means removably arranged inside the upper body to protect the inside of the manhole from the ingress of rainwater.
摘要翻译：本发明涉及一种人孔盖，其具有彼此联接以保持平衡的上主体和下体，以稳定地承受从外部源施加的载荷，以保护人孔内部免受雨水的侵入并且能够使上身稳定地固定在下身内。为了实现上述目的，本发明的关键技术特征涉及一种人孔盖，包括：下体，其内部为中空，沿着中空空间的内表面形成螺旋肋，以及形成在所述螺旋肋的上表面上的凸凹部; 上体，其联接在下体内部，其内部为中空的，具有沿其外表面形成的螺旋肋和凸凹部，以对应于螺旋肋和下部的凸凹部主体和形成在其上表面的台阶部分; 安装在上身的阶梯部分中的盖子，用于保护上身的内部不引入异物; 以及可拆卸地布置在上身内部的防水装置，以保护人孔内部免受雨水的侵入。

6. 发明申请

US20050006695A1 Memory cells with nonuniform floating gate structures and methods of forming the same 失效
标题翻译：具有不均匀浮栅结构的存储单元及其形成方法
公开(公告)号：US20050006695A1
公开(公告)日：2005-01-13
申请号：US10726768
申请日：2003-12-03
申请人： Jae-Duk Lee , Dong-gun Park , Jeong-Hyuk Choi
发明人： Jae-Duk Lee , Dong-gun Park , Jeong-Hyuk Choi
IPC分类号： H01L21/8247 , H01L21/28 , H01L29/423 , H01L29/788
CPC分类号： H01L21/28273 , H01L29/42324 , H01L29/42336 , H01L29/7883
摘要： In a floating gate memory cell including a floating gate separated from an active region by a tunnel isolation region, a first one of the active region and the floating gate comprises a portion that protrudes towards a second one of the active region and the floating gate. In some embodiments, the protruding portion tapers toward the second one of the active region and the floating gate. The tunnel insulation layer may be narrowed at the protruding portion. Protruding portions may be formed on both the floating gate and the active region.
摘要翻译：在包括通过隧道隔离区域与有源区域分离的浮动栅极的浮动栅极存储单元中，有源区域和浮置栅极中的第一个包括朝向有源区域和浮置栅极中的第二个突出的部分。在一些实施例中，突出部分朝向有源区域和浮动栅极中的第二个逐渐变细。隧道绝缘层可以在突出部分变窄。突出部分可以形成在浮动栅极和有源区域两者上。

7. 发明授权

US09887208B2 Vertical memory device 有权
公开(公告)号：US09887208B2
公开(公告)日：2018-02-06
申请号：US15218421
申请日：2016-07-25
申请人： Young Hwan Son , Young Woo Park , Jae Duk Lee
发明人： Young Hwan Son , Young Woo Park , Jae Duk Lee
IPC分类号： H01L27/115 , H01L27/11582 , H01L27/11573 , G11C16/04 , G11C16/26 , G11C16/10 , H01L27/11565 , H01L27/1157 , H01L27/11575
CPC分类号： H01L27/11582 , G11C16/0466 , G11C16/10 , G11C16/26 , H01L27/11565 , H01L27/1157 , H01L27/11573 , H01L27/11575
摘要： A memory device may include a peripheral region and a cell region. The peripheral region may include a first substrate, a plurality of circuit elements disposed on the first substrate, a first insulating layer disposed on the plurality of circuit elements, and a first protective layer disposed in the first insulating layer. The cell region may include a second substrate disposed on the first insulating layer, wherein the cell region includes a first impurity region, a channel region extending in a direction substantially perpendicular to an upper surface of the second substrate, a plurality of gate electrode layers stacked on the second substrate and adjacent to the channel region, and a first contact electrically connected to the first impurity region, wherein the first protective layer is disposed below the first impurity region, and has a shape corresponding to a shape of the first impurity region.

8. 发明申请

US20170365616A1 VERTICAL NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME 审中-公开
公开(公告)号：US20170365616A1
公开(公告)日：2017-12-21
申请号：US15485579
申请日：2017-04-12
申请人： Shin-hwan KANG , Heon-kyu LEE , Kohji KANAMORI , Jae-duk LEE , Jae-hoon JANG , Kwang-soo KIM
发明人： Shin-hwan KANG , Heon-kyu LEE , Kohji KANAMORI , Jae-duk LEE , Jae-hoon JANG , Kwang-soo KIM
IPC分类号： H01L27/11582 , H01L29/04 , H01L27/1157 , H01L27/11524 , H01L21/768 , H01L23/532 , H01L23/528 , H01L23/522 , H01L29/16 , H01L27/11556
CPC分类号： H01L27/11582 , H01L21/76816 , H01L21/76877 , H01L23/5226 , H01L23/528 , H01L23/53271 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11573 , H01L29/04 , H01L29/16
摘要： A vertical non-volatile memory device includes a substrate including a cell region; a lower insulating layer on the substrate; a lower wiring pattern in the cell region having a predetermined pattern and connected to the substrate through the lower insulating layer; and a plurality of vertical channel layers extending in a vertical direction with respect to a top surface of the substrate in the cell region, spaced apart from one another in a horizontal direction with respect to the top surface of the substrate, and electrically connected to the lower wiring pattern. The memory device also includes a plurality of gate electrodes stacked alternately with interlayer insulating layers in the cell region in the vertical direction along a side wall of a vertical channel layer and formed to extend in a first direction along the horizontal direction.

9. 发明申请

US20170133398A1 VERTICAL MEMORY DEVICE 有权
公开(公告)号：US20170133398A1
公开(公告)日：2017-05-11
申请号：US15218421
申请日：2016-07-25
申请人： YOUNG HWAN SON , YOUNG WOO PARK , JAE DUK LEE
发明人： YOUNG HWAN SON , YOUNG WOO PARK , JAE DUK LEE
IPC分类号： H01L27/115 , G11C16/14 , G11C16/10 , G11C16/08 , G11C16/24 , G11C16/26 , H01L23/528 , G11C16/04
CPC分类号： H01L27/11582 , G11C16/0466 , G11C16/10 , G11C16/26 , H01L27/11565 , H01L27/1157 , H01L27/11573 , H01L27/11575
摘要： A memory device may include a peripheral region and a cell region. The peripheral region may include a first substrate, a plurality of circuit elements disposed on the first substrate, a first insulating layer disposed on the plurality of circuit elements, and a first protective layer disposed in the first insulating layer. The cell region may include a second substrate disposed on the first insulating layer, wherein the cell region includes a first impurity region, a channel region extending in a direction substantially perpendicular to an upper surface of the second substrate, a plurality of gate electrode layers stacked on the second substrate and adjacent to the channel region, and a first contact electrically connected to the first impurity region, wherein the first protective layer is disposed below the first impurity region, and has a shape corresponding to a shape of the first impurity region.

10. 发明申请

US20170125540A1 NON-VOLATILE MEMORY DEVICES AND MANUFACTURING METHODS THEREOF 审中-公开
公开(公告)号：US20170125540A1
公开(公告)日：2017-05-04
申请号：US15408017
申请日：2017-01-17
申请人： Jin Taek Park , Young Woo Park , Jae Duk Lee
发明人： Jin Taek Park , Young Woo Park , Jae Duk Lee
IPC分类号： H01L29/51 , H01L21/28 , H01L29/49 , H01L29/423 , H01L27/11556 , H01L27/11582
CPC分类号： H01L29/513 , G11C16/0483 , H01L21/28273 , H01L27/11556 , H01L27/11582 , H01L29/42324 , H01L29/4234 , H01L29/42364 , H01L29/4916 , H01L29/66825 , H01L29/66833 , H01L29/7789 , H01L29/7926
摘要： There is provided a method of manufacturing a non-volatile memory device including: alternatively stacking a plurality of insulating layers and a plurality of conductive layers on a top surface of a substrate; forming an opening that exposes the top surface of the substrate and lateral surfaces of the insulating layers and the conductive layers; forming an anti-oxidation layer on at least the exposed lateral surfaces of the conductive layers; forming a gate dielectric layer on the anti-oxidation layer, the gate dielectric layer including a blocking layer, an electric charge storage layer, and a tunneling layer that are sequentially formed on the anti-oxidation layer; and forming a channel region on the tunneling layer.

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