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1. 发明申请

US20100167496A1 METHOD FOR FORMING DEVICE ISOLATION LAYER OF SEMICONDUCTOR DEVICE AND NON-VOLATILE MEMORY DEVICE 有权
标题翻译：形成半导体器件和非易失性存储器件的器件隔离层的方法
公开(公告)号：US20100167496A1
公开(公告)日：2010-07-01
申请号：US12473307
申请日：2009-05-28
申请人： Jae-Hyoung Koo , Jin-Woong Kim , Mi-Ri Lee , Chi-Ho Kim , Jin-Ho Bin
发明人： Jae-Hyoung Koo , Jin-Woong Kim , Mi-Ri Lee , Chi-Ho Kim , Jin-Ho Bin
IPC分类号： H01L21/762
CPC分类号： H01L21/76232 , H01L27/11521 , H01L27/11568
摘要： A method for forming a device isolation layer of a semiconductor device or a non-volatile memory device is provided. A method for forming a device isolation layer of a semiconductor device includes: forming trenches having a first predetermined depth by etching a substrate; forming a first insulation layer having a second predetermined depth inside the trenches; forming a liner oxide layer having a predetermined thickness on internal walls of the trenches with the first insulation layer formed therein; and forming a second insulation layer for forming a device isolation layer over the substrate with the liner oxide layer formed therein, wherein the second insulation layer has a lower etch rate than that of the first insulation layer.
摘要翻译：提供了一种用于形成半导体器件或非易失性存储器件的器件隔离层的方法。一种用于形成半导体器件的器件隔离层的方法包括：通过蚀刻衬底来形成具有第一预定深度的沟槽; 形成在所述沟槽内具有第二预定深度的第一绝缘层; 在其中形成有第一绝缘层的沟槽的内壁上形成具有预定厚度的衬里氧化物层; 以及形成用于在其上形成有衬里氧化物层的衬底上形成器件隔离层的第二绝缘层，其中所述第二绝缘层具有比所述第一绝缘层的蚀刻速率更低的蚀刻速率。

2. 发明授权

US07592222B2 Method of fabricating flash memory device 失效
标题翻译：制造闪存设备的方法
公开(公告)号：US07592222B2
公开(公告)日：2009-09-22
申请号：US12147178
申请日：2008-06-26
申请人： Eun Shil Park , Kwon Hong , Jae Hong Kim , Jae Hyoung Koo
发明人： Eun Shil Park , Kwon Hong , Jae Hong Kim , Jae Hyoung Koo
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , H01L27/11521
摘要： The present invention relates to a method of fabricating a flash memory device. According to a method of fabricating a flash memory device in accordance with an aspect of the present invention, a semiconductor substrate over which a tunnel insulating layer and a first conductive layer are formed is provided. A first oxide layer is formed on the first conductive layer using a plasma oxidization process in a state where a back bias voltage is applied. A nitride layer is formed on the first oxide layer. A second oxide layer is formed on the nitride layer. A second conductive layer is formed on the second oxide layer.
摘要翻译：本发明涉及一种制造闪速存储器件的方法。根据本发明的一个方面的制造闪速存储器件的方法，提供了形成隧道绝缘层和第一导电层的半导体衬底。在施加反向偏置电压的状态下，使用等离子体氧化工艺在第一导电层上形成第一氧化物层。在第一氧化物层上形成氮化物层。在氮化物层上形成第二氧化物层。在第二氧化物层上形成第二导电层。

3. 发明申请

US20080248637A1 METHOD OF FABRICATING SEMICONDUCTOR DEVICE 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US20080248637A1
公开(公告)日：2008-10-09
申请号：US11962416
申请日：2007-12-21
申请人： Dong Ho Lee , Kwon Hong , Jae Mun Kim , Hee Soo Kim , Jae Hyoung Koo
发明人： Dong Ho Lee , Kwon Hong , Jae Mun Kim , Hee Soo Kim , Jae Hyoung Koo
IPC分类号： H01L21/425
CPC分类号： H01L21/28061 , H01L21/265 , H01L21/324
摘要： In one embodiment, a gate insulating layer, a conductive layer, and a metal layer are formed over a semiconductor substrate. An ion implantation region is formed in an interface of the conductive layer and the metal layer by performing an ion implantation process. A flash annealing process is performed on the ion-implanted semiconductor substrate. The metal layer, the conductive layer, and the gate insulating layer are patterned.
摘要翻译：在一个实施例中，在半导体衬底上形成栅绝缘层，导电层和金属层。通过进行离子注入工艺，在导电层和金属层的界面上形成离子注入区。在离子注入的半导体衬底上进行闪光退火处理。图案化金属层，导电层和栅极绝缘层。

4. 发明申请

US20130244394A1 METHOD FOR FABRICATING CAPACITOR WITH HIGH ASPECT RATIO 有权
标题翻译：高比例电容器制作方法
公开(公告)号：US20130244394A1
公开(公告)日：2013-09-19
申请号：US13494400
申请日：2012-06-12
申请人： Beom-Yong KIM , Kee-Jeung LEE , Yun-Hyuck JI , Seung-Mi LEE , Jae-Hyoung KOO , Kwan-Woo DO , Kyung-Woong PARK , Ji-Hoon AHN , Woo-Young PARK
发明人： Beom-Yong KIM , Kee-Jeung LEE , Yun-Hyuck JI , Seung-Mi LEE , Jae-Hyoung KOO , Kwan-Woo DO , Kyung-Woong PARK , Ji-Hoon AHN , Woo-Young PARK
IPC分类号： H01L21/02 , H01L21/20
CPC分类号： H01L28/91 , H01L27/10852
摘要： A method for fabricating a capacitor includes: forming a first silicon layer over a semiconductor substrate, where the first silicon layer is doped with a dopant; forming an undoped second silicon layer over the first silicon layer; forming an opening by etching the second silicon layer and the first silicon layer; forming a storage node in the opening; and removing the first silicon layer and the second silicon layer.
摘要翻译：制造电容器的方法包括：在半导体衬底上形成第一硅层，其中所述第一硅层掺杂有掺杂剂; 在所述第一硅层上形成未掺杂的第二硅层; 通过蚀刻第二硅层和第一硅层形成开口; 在开口中形成存储节点; 以及去除所述第一硅层和所述第二硅层。

5. 发明授权

US07674696B2 Method of fabricating semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US07674696B2
公开(公告)日：2010-03-09
申请号：US11962416
申请日：2007-12-21
申请人： Dong Ho Lee , Kwon Hong , Jae Mun Kim , Hee Soo Kim , Jae Hyoung Koo
发明人： Dong Ho Lee , Kwon Hong , Jae Mun Kim , Hee Soo Kim , Jae Hyoung Koo
IPC分类号： H01L21/425
CPC分类号： H01L21/28061 , H01L21/265 , H01L21/324
摘要： In one embodiment, a gate insulating layer, a conductive layer, and a metal layer are formed over a semiconductor substrate. An ion implantation region is formed in an interface of the conductive layer and the metal layer by performing an ion implantation process. A flash annealing process is performed on the ion-implanted semiconductor substrate. The metal layer, the conductive layer, and the gate insulating layer are patterned.
摘要翻译：在一个实施例中，在半导体衬底上形成栅绝缘层，导电层和金属层。通过进行离子注入工艺，在导电层和金属层的界面上形成离子注入区。在离子注入的半导体衬底上进行闪光退火处理。图案化金属层，导电层和栅极绝缘层。

6. 发明申请

US20090124096A1 METHOD OF FABRICATING FLASH MEMORY DEVICE 审中-公开
标题翻译：制造闪存存储器件的方法
公开(公告)号：US20090124096A1
公开(公告)日：2009-05-14
申请号：US12164011
申请日：2008-06-28
申请人： Jae Hyoung Koo , Kwon Hong , Jae Hong Kim , Eun Shil Park
发明人： Jae Hyoung Koo , Kwon Hong , Jae Hong Kim , Eun Shil Park
IPC分类号： H01L21/31
CPC分类号： H01L21/02238 , H01L21/0214 , H01L21/02164 , H01L21/0217 , H01L21/022 , H01L21/02247 , H01L21/02252 , H01L21/02255 , H01L21/02326 , H01L21/02332 , H01L21/02337 , H01L21/0234 , H01L21/3143 , H01L27/11517 , H01L29/40114
摘要： The present invention relates to a method of fabricating a flash memory device, the method of the present invention comprises the steps of forming a tunnel insulating layer on a semiconductor substrate through a plasma oxidation process and performing a nitridation treatment to a surface of the tunnel insulating layer.
摘要翻译：本发明涉及一种制造闪速存储器件的方法，本发明的方法包括以下步骤：通过等离子体氧化工艺在半导体衬底上形成隧道绝缘层，并对隧道绝缘层的表面进行氮化处理层。

7. 发明授权

US07507644B2 Method of forming dielectric layer of flash memory device 失效
标题翻译：形成闪存器件介电层的方法
公开(公告)号：US07507644B2
公开(公告)日：2009-03-24
申请号：US11489230
申请日：2006-07-19
申请人： Jae Hyoung Koo
发明人： Jae Hyoung Koo
IPC分类号： H01L21/20
CPC分类号： H01L21/28273 , H01L29/513
摘要： A method of manufacturing a flash memory device, wherein according to one embodiment, when a high dielectric material is formed by a remote plasma atomic layer deposition method, first and second dielectric layers are formed by one process at the same time using silicate as the first dielectric layer and the high dielectric layer formed on the silicate as the second dielectric layer. Accordingly, cost can be saved since the process is shortened, a film quality better than that of the existing dielectric layer structure can be obtained, and a film with improved step coverage can be formed. Furthermore, capacitance and insulating breakdown voltage can be increased by using silicate having a high dielectric constant and a high dielectric layer.
摘要翻译：一种制造闪存器件的方法，其中根据一个实施例，当通过远程等离子体原子层沉积方法形成高电介质材料时，通过一个工艺同时使用硅酸盐作为第一电介质层形成第一和第二电介质层电介质层和形成在硅酸盐上的高介电层作为第二介电层。因此，可以节省成本，因为缩短了工艺，可以获得比现有的电介质层结构更好的膜质量，并且可以形成具有改善的台阶覆盖率的膜。此外，通过使用具有高介电常数和高介电层的硅酸盐，可以提高电容和绝缘击穿电压。

8. 发明申请

US20160181425A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20160181425A1
公开(公告)日：2016-06-23
申请号：US14959457
申请日：2015-12-04
申请人： Keun Hee BAI , Kyoung Hwan YEO , Seung Seok HA , Seung Ju PARK , Do Hyoung KIM , Myeong Cheol KIM , Jae Hyoung KOO , Ki Byung PARK
发明人： Keun Hee BAI , Kyoung Hwan YEO , Seung Seok HA , Seung Ju PARK , Do Hyoung KIM , Myeong Cheol KIM , Jae Hyoung KOO , Ki Byung PARK
IPC分类号： H01L29/78 , H01L29/165 , H01L29/161 , H01L29/66 , H01L29/06
CPC分类号： H01L29/7848 , H01L29/165 , H01L29/66545 , H01L29/66818 , H01L29/7851
摘要： There is provided a method for manufacturing a semiconductor device including a substrate including a plurality of active regions, a plurality of gate electrodes extending in a first direction to intersect a portion of the plurality of active regions, and including first and second gate electrodes disposed to be adjacent to each other in the first direction, a gate isolation portion disposed between the first and second gate electrodes. The gate isolation portion includes a first layer and second layers disposed on both ends of the first layer in a second direction perpendicular to the first direction.
摘要翻译：提供了一种制造半导体器件的方法，该半导体器件包括：包括多个有源区的衬底;沿第一方向延伸以与多个有源区的一部分相交的多个栅电极，并且包括设置到在第一方向上彼此相邻，设置在第一和第二栅极之间的栅极隔离部分。栅极隔离部分包括在垂直于第一方向的第二方向上设置在第一层的两端上的第一层和第二层。

9. 发明授权

US08278185B2 Method for forming device isolation layer of semiconductor device and non-volatile memory device 有权
标题翻译：用于形成半导体器件和非易失性存储器件的器件隔离层的方法
公开(公告)号：US08278185B2
公开(公告)日：2012-10-02
申请号：US12473307
申请日：2009-05-28
申请人： Jae-Hyoung Koo , Jin-Woong Kim , Mi-Ri Lee , Chi-Ho Kim , Jin-Ho Bin
发明人： Jae-Hyoung Koo , Jin-Woong Kim , Mi-Ri Lee , Chi-Ho Kim , Jin-Ho Bin
IPC分类号： H01L21/76
CPC分类号： H01L21/76232 , H01L27/11521 , H01L27/11568
摘要： A method for forming a device isolation layer of a semiconductor device or a non-volatile memory device is provided. A method for forming a device isolation layer of a semiconductor device includes: forming trenches having a first predetermined depth by etching a substrate; forming a first insulation layer having a second predetermined depth inside the trenches; forming a liner oxide layer having a predetermined thickness on internal walls of the trenches with the first insulation layer formed therein; and forming a second insulation layer for forming a device isolation layer over the substrate with the liner oxide layer formed therein, wherein the second insulation layer has a lower etch rate than that of the first insulation layer.
摘要翻译：提供了一种用于形成半导体器件或非易失性存储器件的器件隔离层的方法。一种用于形成半导体器件的器件隔离层的方法包括：通过蚀刻衬底来形成具有第一预定深度的沟槽; 形成在所述沟槽内具有第二预定深度的第一绝缘层; 在其中形成有第一绝缘层的沟槽的内壁上形成具有预定厚度的衬里氧化物层; 以及形成用于在其上形成有衬里氧化物层的衬底上形成器件隔离层的第二绝缘层，其中所述第二绝缘层具有比所述第一绝缘层的蚀刻速率更低的蚀刻速率。

10. 发明授权

US07795123B2 Method of forming gate electrode 失效
标题翻译：形成栅电极的方法
公开(公告)号：US07795123B2
公开(公告)日：2010-09-14
申请号：US12345832
申请日：2008-12-30
申请人： Eun Shil Park , Kwon Hong , Jae Hong Kim , Jae Hyoung Koo
发明人： Eun Shil Park , Kwon Hong , Jae Hong Kim , Jae Hyoung Koo
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L21/28035 , H01L21/02576 , H01L21/0262 , H01L29/4925
摘要： The present invention discloses to a method of forming a gate electrode, the method according to the present invention comprises the steps of forming a lower amorphous silicon layer using silane (SiH4) gas and nitrous oxide (N2O) gas; forming an upper amorphous silicon layer on the lower amorphous silicon layer; and crystallizing the lower and upper amorphous silicon layers through a thermal process.
摘要翻译：本发明公开了一种形成栅电极的方法，根据本发明的方法包括以下步骤：使用硅烷（SiH4）气和一氧化二氮（N2O）气形成下一非晶硅层; 在所述下部非晶硅层上形成上部非晶硅层; 并通过热过程使下部和上部非晶硅层结晶。

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