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1. 发明授权

US08581650B2 Duty cycle correction circuit and delay locked loop circuit including the same 有权
标题翻译：占空比校正电路和延迟锁相环电路包括相同
公开(公告)号：US08581650B2
公开(公告)日：2013-11-12
申请号：US13563863
申请日：2012-08-01
申请人： Ki Han Kim , Ja Beom Koo
发明人： Ki Han Kim , Ja Beom Koo
IPC分类号： H03K3/017
CPC分类号： H03L7/089
摘要： A duty cycle correction circuit includes: a duty cycle correction unit configured to correct a duty cycle of an input clock signal according to a duty cycle correction code and generate an output clock signal; a duty cycle detection section configured to detect a duty cycle of the output clock signal and generate an up-down signal; a noise detection signal generation section configured to detect a variation of the up-down signal and generate the noise detection signal; and a duty cycle correction control unit configured to generate the duty cycle correction code in response to the noise detection signal and the up-down signal.
摘要翻译：占空比校正电路包括：占空比校正单元，被配置为根据占空比校正码校正输入时钟信号的占空比，并生成输出时钟信号; 占空比检测部，被配置为检测所述输出时钟信号的占空比并产生上下信号; 噪声检测信号生成部，被配置为检测所述上下信号的变化并生成所述噪声检测信号; 以及占空比校正控制单元，被配置为响应于噪声检测信号和上下信号产生占空比校正码。

2. 发明申请

US20220197487A1 VIEW MODE CHANGE DEVICE USING TOUCH PATTERN INPUT AND METHOD THEREFOR 有权
公开(公告)号：US20220197487A1
公开(公告)日：2022-06-23
申请号：US17606085
申请日：2020-06-19
申请人： Ja Beom KOO
发明人： Ja Beom KOO
IPC分类号： G06F3/04845 , G06F3/0488 , G06F1/16 , H04M1/72454
摘要： The present invention relates to a view mode change device for rotating or fixing a displayed content by using a specific pattern according to simultaneous movements of a first touch and a second touch, and a method therefor, the view mode change device comprising a touch panel; a pattern sensing unit for sensing a first touch with a specific time duration in one area of the touch panel, sensing a second touch with a specific time duration in the other area of the touch panel, and sensing a specific pattern according to simultaneous movements of the first touch and the second touch; and a screen control unit for rotating or fixing, by the specific pattern, a content being displayed on the touch panel.

3. 发明授权

US07986177B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07986177B2
公开(公告)日：2011-07-26
申请号：US12494355
申请日：2009-06-30
申请人： Ja-Beom Koo , Dong-Suk Shin
发明人： Ja-Beom Koo , Dong-Suk Shin
IPC分类号： H03L7/06
CPC分类号： H03L7/0812 , H03K5/133 , H03K2005/00026 , H03L7/087
摘要： A semiconductor device, includes a clock delay unit configured to include a plurality of delay units connected in series, where the delay amount of each delay unit varies depending on a level of a control voltage, for delaying a source clock to generate a feedback clock and mixing clocks outputted from the respective delay units to generate a frequency multiplication clock, a harmonic lock determination unit configured to determine whether a harmonic lock has occurred based on a frequency difference between the source clock and the frequency multiplication clock, and a control voltage generator configured to adjust a level of the control voltage based on a phase difference between the source clock and the feedback clock and a determination result of the harmonic lock determination unit.
摘要翻译：一种半导体器件，包括：时钟延迟单元，被配置为包括串联连接的多个延迟单元，其中每个延迟单元的延迟量根据控制电压的电平而变化，用于延迟源时钟以产生反馈时钟; 从相应的延迟单元输出的混合时钟以产生倍频时钟;谐波锁定确定单元，被配置为基于源时钟和倍频时钟之间的频率差来确定是否发生了谐波锁定;以及控制电压发生器，基于源时钟和反馈时钟之间的相位差以及谐波锁定确定单元的确定结果来调节控制电压的电平。

4. 发明申请

US20130154702A1 DUTY CYCLE CORRECTION CIRCUIT AND DELAY LOCKED LOOP CIRCUIT INCLUDING THE SAME 有权
标题翻译：占空比校正电路和延迟锁定环路包括其中
公开(公告)号：US20130154702A1
公开(公告)日：2013-06-20
申请号：US13563863
申请日：2012-08-01
申请人： Ki Han KIM , Ja Beom KOO
发明人： Ki Han KIM , Ja Beom KOO
IPC分类号： H03L7/089
CPC分类号： H03L7/089
摘要： A duty cycle correction circuit includes: a duty cycle correction unit configured to correct a duty cycle of an input clock signal according to a duty cycle correction code and generate an output clock signal; a duty cycle detection section configured to detect a duty cycle of the output clock signal and generate an up-down signal; a noise detection signal generation section configured to detect a variation of the up-down signal and generate the noise detection signal; and a duty cycle correction control unit configured to generate the duty cycle correction code in response to the noise detection signal and the up-down signal.
摘要翻译：占空比校正电路包括：占空比校正单元，被配置为根据占空比校正码校正输入时钟信号的占空比，并生成输出时钟信号; 占空比检测部，被配置为检测所述输出时钟信号的占空比并产生上下信号; 噪声检测信号生成部，被配置为检测所述上下信号的变化并生成所述噪声检测信号; 以及占空比校正控制单元，被配置为响应于噪声检测信号和上下信号产生占空比校正码。

5. 发明申请

US20120007631A1 INTEGRATED CIRCUIT AND METHOD FOR CONTROLLING DATA OUTPUT IMPEDANCE 有权
标题翻译：用于控制数据输出阻抗的集成电路和方法
公开(公告)号：US20120007631A1
公开(公告)日：2012-01-12
申请号：US13033845
申请日：2011-02-24
申请人： Ja Beom KOO , Kwan Weon KIM
发明人： Ja Beom KOO , Kwan Weon KIM
IPC分类号： H03K19/003
CPC分类号： G11C7/1051 , G11C7/1057 , G11C7/1072 , G11C8/08 , G11C29/02 , G11C29/022 , G11C29/028 , G11C29/50008 , G11C2207/2254
摘要： An integrated circuit for controlling data output impedance includes an address decoder, a selection signal decoder, and a transfer control unit. The address decoder is configured to decode an address signal and generate a selection mode signal and a first adjustment mode signal. The selection signal decoder is configured to decode a selection signal and generate an enable signal and a disable signal. The transfer control unit is configured to transfer a pull-up signal and a pull-down signal as a selection pull-up signal and a selection pull-down signal.
摘要翻译：用于控制数据输出阻抗的集成电路包括地址解码器，选择信号解码器和传送控制单元。地址解码器被配置为解码地址信号并产生选择模式信号和第一调整模式信号。选择信号解码器被配置为对选择信号进行解码并产生使能信号和禁用信号。传送控制单元被配置为传送上拉信号和下拉信号作为选择上拉信号和选择下拉信号。

6. 发明申请

US20100164573A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20100164573A1
公开(公告)日：2010-07-01
申请号：US12494355
申请日：2009-06-30
申请人： Ja-Beom Koo , Dong-Suk Shin
发明人： Ja-Beom Koo , Dong-Suk Shin
IPC分类号： H03L7/06
CPC分类号： H03L7/0812 , H03K5/133 , H03K2005/00026 , H03L7/087
摘要： A semiconductor device, includes a clock delay unit configured to include a plurality of delay units connected in series, where the delay amount of each delay unit varies depending on a level of a control voltage, for delaying a source clock to generate a feedback clock and mixing clocks outputted from the respective delay units to generate a frequency multiplication clock, a harmonic lock determination unit configured to determine whether a harmonic lock has occurred based on a frequency difference between the source clock and the frequency multiplication clock, and a control voltage generator configured to adjust a level of the control voltage based on a phase difference between the source clock and the feedback clock and a determination result of the harmonic lock determination unit.
摘要翻译：一种半导体器件，包括：时钟延迟单元，被配置为包括串联连接的多个延迟单元，其中每个延迟单元的延迟量根据控制电压的电平而变化，用于延迟源时钟以产生反馈时钟; 从相应的延迟单元输出的混合时钟以产生倍频时钟;谐波锁定确定单元，被配置为基于源时钟和倍频时钟之间的频率差来确定是否发生了谐波锁定;以及控制电压发生器，基于源时钟和反馈时钟之间的相位差以及谐波锁定确定单元的确定结果来调节控制电压的电平。

7. 发明授权

US08237464B2 Integrated circuit and method for controlling data output impedance 有权
标题翻译：用于控制数据输出阻抗的集成电路和方法
公开(公告)号：US08237464B2
公开(公告)日：2012-08-07
申请号：US13033845
申请日：2011-02-24
申请人： Ja Beom Koo , Kwan Weon Kim
发明人： Ja Beom Koo , Kwan Weon Kim
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： G11C7/1051 , G11C7/1057 , G11C7/1072 , G11C8/08 , G11C29/02 , G11C29/022 , G11C29/028 , G11C29/50008 , G11C2207/2254
摘要： An integrated circuit for controlling data output impedance includes an address decoder, a selection signal decoder, and a transfer control unit. The address decoder is configured to decode an address signal and generate a selection mode signal and a first adjustment mode signal. The selection signal decoder is configured to decode a selection signal and generate an enable signal and a disable signal. The transfer control unit is configured to transfer a pull-up signal and a pull-down signal as a selection pull-up signal and a selection pull-down signal.
摘要翻译：用于控制数据输出阻抗的集成电路包括地址解码器，选择信号解码器和传送控制单元。地址解码器被配置为解码地址信号并产生选择模式信号和第一调整模式信号。选择信号解码器被配置为对选择信号进行解码并产生使能信号和禁用信号。传送控制单元被配置为传送上拉信号和下拉信号作为选择上拉信号和选择下拉信号。

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