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1. 发明申请

WO2009033147A2 POWER EFFICIENT BATCH-FRAME AUDIO DECODING APPARATUS, SYSTEM AND METHOD 审中-公开
标题翻译：功率高效的分批帧音频解码装置，系统和方法
公开(公告)号：WO2009033147A2
公开(公告)日：2009-03-12
申请号：PCT/US2008/075578
申请日：2008-09-08
申请人： QUALCOMM INCORPORATED , YOO, Heejong , KAMATH, Nidish Ramachandra , CHOY, Eddie L.T. , JOHN, Johnny Kallacheril , GUPTA, Samir Kumar
发明人： YOO, Heejong , KAMATH, Nidish Ramachandra , CHOY, Eddie L.T. , JOHN, Johnny Kallacheril , GUPTA, Samir Kumar
CPC分类号： G10L19/16 , G06F1/3203 , G06F3/162 , H04W52/0274
摘要： Power savings in a mobile device is accomplished by generating audio samples by decoding a bitstream with a decoding system within the mobile device. The generated audio samples are transferred into at least one memory bank in a set of memory banks in a power saver block within the mobile device. Parts of the decoding system not involved in the storing of the generated audio samples are switched off after batch decoding a bitstream associated with multiple audio frames. The bitstream includes bits less than that found in one audio file. At least one of the memory banks in the set of memory banks is power collapsible. The fetching of the decoded by the decoding system can be synchronized with a paging channel of a modem in the mobile device. The transferred audio samples is a lossless compression and may occur after a re-encoding.
摘要翻译：移动设备中的功率节省通过利用移动设备内的解码系统对比特流进行解码来生成音频样本来实现。产生的音频采样被传送到移动设备内的节电器块中的一组存储体中的至少一个存储体中。在批量解码与多个音频帧相关联的比特流之后，不涉及存储生成的音频样本的部分解码系统被关闭。比特流包括比在一个音频文件中找到的比特少的比特。该组存储体中的至少一个存储体是可折叠的。由解码系统解码的解码可以与移动设备中的调制解调器的寻呼信道同步。传输的音频样本是无损压缩的，可能会在重新编码之后发生。

2. 发明申请

WO2009033147A3 POWER EFFICIENT BATCH-FRAME AUDIO DECODING APPARATUS, SYSTEM AND METHOD 审中-公开
标题翻译：功率有效的批量音频解码设备，系统和方法
公开(公告)号：WO2009033147A3
公开(公告)日：2009-05-28
申请号：PCT/US2008075578
申请日：2008-09-08
申请人： QUALCOMM INC , YOO HEEJONG , KAMATH NIDISH RAMACHANDRA , CHOY EDDIE L T , JOHN JOHNNY KALLACHERIL , GUPTA SAMIR KUMAR
发明人： YOO HEEJONG , KAMATH NIDISH RAMACHANDRA , CHOY EDDIE L T , JOHN JOHNNY KALLACHERIL , GUPTA SAMIR KUMAR
IPC分类号： G06F1/32 , G06F3/16 , G06F5/06 , G10L19/14 , H04W52/02
CPC分类号： G10L19/16 , G06F1/3203 , G06F3/162 , H04W52/0274 , Y02D70/00
摘要： Power savings in a mobile device is accomplished by generating audio samples by decoding a bitstream with a decoding system within the mobile device. The generated audio samples are transferred into at least one memory bank in a set of memory banks in a power saver block within the mobile device. Parts of the decoding system not involved in the storing of the generated audio samples are switched off after batch decoding a bitstream associated with multiple audio frames. The bitstream includes bits less than that found in one audio file. At least one of the memory banks in the set of memory banks is power collapsible. The fetching of the decoded by the decoding system can be synchronized with a paging channel of a modem in the mobile device. The transferred audio samples is a lossless compression and may occur after a re-encoding.
摘要翻译：移动设备中的功率节省通过利用移动设备内的解码系统对比特流进行解码来生成音频样本来实现。生成的音频样本被传送到移动设备内的节电块中的一组存储器组中的至少一个存储体。在对与多个音频帧相关联的比特流进行批量解码之后，不涉及生成的音频样本的存储的部分解码系统被关闭。比特流包括比在一个音频文件中发现的比特小的比特。存储器组中的至少一个存储体是电源可折叠的。由解码系统解码的提取可以与移动设备中的调制解调器的寻呼信道同步。传输的音频样本是无损压缩，并且可能在重新编码之后发生。

3. 发明申请

WO2007084925A3 METHOD AND APPARATUS FOR DEBUGGING A MULTICORE SYSTEM 审中-公开
标题翻译：用于调制多系统的方法和装置
公开(公告)号：WO2007084925A3
公开(公告)日：2007-11-22
申请号：PCT/US2007060645
申请日：2007-01-17
申请人： QUALCOMM INC , JOHN JOHNNY KALLACHERIL
发明人： JOHN JOHNNY KALLACHERIL
IPC分类号： G06F11/267
CPC分类号： G06F11/2236
摘要： Techniques for debugging a multicore system with synchronous stop and resume capabilities are described. In one design, an apparatus (e.g., an ASIC) includes first and second processing cores. During debugging, the first or second processing core receives a software command to stop operation and generates a first hardware signal indicating the stop. The other processing core receives the first hardware signal and stops operation. Both processing cores stop at approximately the same time based on the first hardware signal. Thereafter, the first or second processing core receives another software command to resume operation and generates a second hardware signal indicating resumption of operation. The other processing core receives the second hardware signal and resumes operation. Both processing cores resume at approximately the same time based on the second hardware signal. The first and second hardware signals may come from the same or different processing cores.
摘要翻译：描述了用于调试具有同步停止和恢复功能的多核系统的技术。在一种设计中，装置（例如，ASIC）包括第一和第二处理核。在调试期间，第一或第二处理核心接收软件命令以停止操作并产生指示停止的第一硬件信号。另一个处理核心接收第一个硬件信号并停止运行。两个处理核心基于第一个硬件信号在大致相同的时间停止。此后，第一或第二处理核心接收另一软件命令以恢复操作，并产生指示恢复操作的第二硬件信号。另一个处理核心接收第二个硬件信号并恢复运行。基于第二硬件信号，两个处理核心在大致相同的时间恢复。第一和第二硬件信号可以来自相同或不同的处理核心。

4. 发明申请

WO2007084925A2 METHOD AND APPARATUS FOR DEBUGGING A MULTICORE SYSTEM 审中-公开
标题翻译：用于调试多核系统的方法和设备
公开(公告)号：WO2007084925A2
公开(公告)日：2007-07-26
申请号：PCT/US2007/060645
申请日：2007-01-17
申请人： QUALCOMM INCORPORATED , JOHN, Johnny Kallacheril
发明人： JOHN, Johnny Kallacheril
IPC分类号： G06F11/267
CPC分类号： G06F11/2236
摘要： Techniques for debugging a multicore system with synchronous stop and resume capabilities are described. In one design, an apparatus (e.g., an ASIC) includes first and second processing cores. During debugging, the first or second processing core receives a software command to stop operation and generates a first hardware signal indicating the stop. The other processing core receives the first hardware signal and stops operation. Both processing cores stop at approximately the same time based on the first hardware signal. Thereafter, the first or second processing core receives another software command to resume operation and generates a second hardware signal indicating resumption of operation. The other processing core receives the second hardware signal and resumes operation. Both processing cores resume at approximately the same time based on the second hardware signal. The first and second hardware signals may come from the same or different processing cores.
摘要翻译：描述了用于调试具有同步停止和恢复能力的多核系统的技术。在一种设计中，装置（例如，ASIC）包括第一和第二处理核心。在调试期间，第一或第二处理核心接收软件命令以停止操作并且生成指示停止的第一硬件信号。另一个处理内核接收第一个硬件信号并停止操作。基于第一个硬件信号，两个处理内核几乎同时停止。此后，第一或第二处理核心接收另一软件命令以恢复操作并产生指示恢复操作的第二硬件信号。另一个处理内核接收第二个硬件信号并恢复操作。两个处理内核都基于第二个硬件信号大致同时恢复。第一个和第二个硬件信号可能来自相同或不同的处理核心。

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