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    • 1. 发明授权
    • Laminated capacitor having laminated internal conductor layers with lead out portions on side areas thereof
    • 层叠电容器,其层叠内部导体层,其侧面区域具有引出部分
    • US07460354B2
    • 2008-12-02
    • US11733685
    • 2007-04-10
    • Masayuki ShimizuIwao FujikawaKazuyuki Shibuya
    • Masayuki ShimizuIwao FujikawaKazuyuki Shibuya
    • H01G4/005H01G4/228
    • H01G4/012H01G4/232H01G4/30
    • One inventive aspect relates to a laminated capacitor capable of satisfying higher electrostatic capacitance and lower ESL at the same time. A dielectric chip constituting the laminated capacitor has an integral structure formed by alternately laminating a pair of first inner conductor layer and second inner conductor layer which are positioned on the same plane and are held in a non-contact relation, and a pair of third inner conductor layer and fourth inner conductor layer which are positioned on the same plane and are held in a non-contact relation, while a dielectric layer is interposed between the pair of first and second inner conductor layers and the pair of third and fourth inner conductor layers. Voltage of one polarity is applied to the first and fourth inner conductor layers from a first outer electrode through lead-out portions, and voltage of the other polarity is applied to the second and third inner conductor layers from a second outer electrode through lead-out portions.
    • 一个发明方面涉及能够同时满足更高静电电容和降低ESL的层叠电容器。 构成层叠电容器的电介质芯片具有通过交替层叠位于同一平面上并保持非接触关系的一对第一内导体层和第二内导体层而形成的一体结构,以及一对第三内导体 导体层和第四内导体层,其位于同一平面上并且保持非接触关系,同时电介质层插入在所述一对第一和第二内部导体层之间,并且所述一对第三和第四内部导体层 。 从第一外部电极通过引出部分将一个极性的电压施加到第一和第四内部导体层,另一个极性的电压从第二外部电极通过引出线施加到第二和第三内部导体层 部分。
    • 2. 发明申请
    • LAMINATED CAPACITOR
    • 层压电容器
    • US20070247783A1
    • 2007-10-25
    • US11733685
    • 2007-04-10
    • Masayuki ShimizuIwao FujikawaKazuyuki Shibuya
    • Masayuki ShimizuIwao FujikawaKazuyuki Shibuya
    • H01G4/005
    • H01G4/012H01G4/232H01G4/30
    • One inventive aspect relates to a laminated capacitor capable of satisfying higher electrostatic capacitance and lower ESL at the same time. A dielectric chip constituting the laminated capacitor has an integral structure formed by alternately laminating a pair of first inner conductor layer and second inner conductor layer which are positioned on the same plane and are held in a non-contact relation, and a pair of third inner conductor layer and fourth inner conductor layer which are positioned on the same plane and are held in a non-contact relation, while a dielectric layer is interposed between the pair of first and second inner conductor layers and the pair of third and fourth inner conductor layers. Voltage of one polarity is applied to the first and fourth inner conductor layers from a first outer electrode through lead-out portions, and voltage of the other polarity is applied to the second and third inner conductor layers from a second outer electrode through lead-out portions.
    • 一个发明方面涉及能够同时满足更高静电电容和降低ESL的层叠电容器。 构成层叠电容器的电介质芯片具有通过交替层叠位于同一平面上并保持非接触关系的一对第一内导体层和第二内导体层而形成的一体结构,以及一对第三内导体 导体层和第四内导体层,其位于同一平面上并且保持非接触关系,同时电介质层插入在所述一对第一和第二内部导体层之间,并且所述一对第三和第四内部导体层 。 从第一外部电极通过引出部分将一个极性的电压施加到第一和第四内部导体层,另一个极性的电压从第二外部电极通过引出线施加到第二和第三内部导体层 部分。