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1. 发明申请

US20060090106A1 Generalized BIST for multiport memories 审中-公开
标题翻译：广播BIST多端口记忆
公开(公告)号：US20060090106A1
公开(公告)日：2006-04-27
申请号：US10974450
申请日：2004-10-27
申请人： Donald Evans , Ilyoung Kim
发明人： Donald Evans , Ilyoung Kim
IPC分类号： G11C29/00
CPC分类号： G11C29/1201 , G11C8/16 , G11C29/12 , G11C29/48
摘要： A generalized hardware architecture that supports built-in self testing (BIST) for a range of different computer memory configurations and a generalized BIST algorithm can be compiled, based on specified configuration characteristics (e.g., the number of write ports, the number of read ports, the number of entries, and the number of bits per entry in the computer memory), to generate the hardware design for a particular computer memory system. In one embodiment, the generalized hardware architecture includes a multiplexer block that enables a single BIST comparator to be multiplexed for use in performing BIST testing via different read ports of the computer memory.
摘要翻译：可以根据指定的配置特性（例如，写入端口数量，读取端口数量）编译支持内置自检（BIST）的广泛的不同计算机内存配置和广义BIST算法的通用硬件体系结构，条目数，以及计算机存储器中每个条目的位数），以生成特定计算机存储器系统的硬件设计。在一个实施例中，广义硬件架构包括多路复用器块，其使单个BIST比较器能够被复用以用于通过计算机存储器的不同读取端口执行BIST测试。

2. 发明授权

US06397349B2 Built-in self-test and self-repair methods and devices for computer memories comprising a reconfiguration memory device 有权
标题翻译：内置的自检和自修复方法和用于计算机存储器的装置，包括重新配置存储器件
公开(公告)号：US06397349B2
公开(公告)日：2002-05-28
申请号：US09170353
申请日：1998-10-13
申请人： Frank P. Higgins , Ilyoung Kim , Goh Komoriya , Hai Quang Pham , Yervant Zorian
发明人： Frank P. Higgins , Ilyoung Kim , Goh Komoriya , Hai Quang Pham , Yervant Zorian
IPC分类号： G06F1300
CPC分类号： G11C29/70
摘要： A reconfiguration memory device is provided associated with a main memory array. The reconfiguration memory device generates a spare address in real time corresponding to a faulty address. The reconfiguration memory device is coupled to an address line, so that when address information is received for the main memory array, the address information is also received by the reconfiguration memory device. The reconfiguration memory device is adapted to send an output signal that results in the address in the spare memory address array being addressed, if the received address information corresponds to a stored faulty address. The output signal includes a spare control signal that directs components to look to the output of the spare memory.
摘要翻译：提供了与主存储器阵列相关联的重新配置存储器件。重新配置存储器装置对应于故障地址实时生成备用地址。重新配置存储器件耦合到地址线，使得当为主存储器阵列接收地址信息时，地址信息也被重新配置存储器件接收。如果接收到的地址信息对应于存储的故障地址，则重新配置存储器设备适于发送导致备用存储器地址阵列中的地址被寻址的输出信号。输出信号包括一个备用控制信号，它指示组件查看备用存储器的输出。

3. 发明授权

US06317846B1 System and method for detecting faults in computer memories using a look up table 有权
标题翻译：使用查找表检测计算机存储器中的故障的系统和方法
公开(公告)号：US06317846B1
公开(公告)日：2001-11-13
申请号：US09170351
申请日：1998-10-13
申请人： Frank P. Higgins , Ilyoung Kim , Yervant Zorian
发明人： Frank P. Higgins , Ilyoung Kim , Yervant Zorian
IPC分类号： G06F1300
CPC分类号： G11C29/44 , G11C29/76
摘要： A method is provided for determining the location of faulty components in a computer memory array on a chip and for providing a software repair procedure. According to the method, the location of faulty components in a computer memory array is determined by successively reading and writing to locations in the array according to an algorithm. If a faulty component is detected, it is determined whether a spare component in a spare memory array on the chip is available. If a spare component is available, a spare component is designated to correspond to the faulty component. A look up table on the same chip stores information representing the location of the faulty component associated with information representing the location of the corresponding spare component. The method may also include, testing the memory array by successively reading and writing to locations on the memory array according to an algorithm, during which step, when a faulty component with which a spare component is associated is addressed, the look up table is used to identify the spare component corresponding to the faulty component, and the spare component is addressed.
摘要翻译：提供了一种用于确定芯片上计算机存储器阵列中的故障组件的位置并提供软件修复过程的方法。根据该方法，通过根据算法连续读取和写入阵列中的位置来确定计算机存储器阵列中的故障组件的位置。如果检测到故障组件，则确定芯片上的备用存储器阵列中的备用组件是否可用。如果备用组件可用，则指定备用组件对应于故障组件。相同芯片上的查找表存储表示与表示相应备用组件的位置的信息相关联的故障组件的位置的信息。该方法还可以包括：根据一种算法连续读取和写入存储器阵列上的位置来测试存储器阵列，在该步骤期间，当寻址与备用组件相关联的故障组件时，使用查找表以识别与故障组件相对应的备用组件，并且寻址备用组件。

4. 发明授权

US06175936B1 Apparatus for detecting faults in multiple computer memories 失效
标题翻译：用于检测多台计算机存储器中的故障的装置
公开(公告)号：US06175936B1
公开(公告)日：2001-01-16
申请号：US09118295
申请日：1998-07-17
申请人： Frank P. Higgins , Ilyoung Kim
发明人： Frank P. Higgins , Ilyoung Kim
IPC分类号： G11C2900
CPC分类号： G11C29/72 , G11C29/14
摘要： Memory test hardware is provided for generating signals for testing a first memory array and a second memory array. The first memory array and the second memory array may be any two of main memory array, a spare memory array, and reconfiguration memory array, or the apparatus may be adapted for testing all three memory arrays. The memory test hardware may include a controller for generating control signals, a data generator coupled to the controller for generating data signals, and an address generator coupled to the controller for generating address signals. The test device may further include an output data evaluator and repair unit for receiving signals from the main memory array and the spare memory array and for detecting faults in those arrays.
摘要翻译：存储器测试硬件被提供用于产生用于测试第一存储器阵列和第二存储器阵列的信号。第一存储器阵列和第二存储器阵列可以是主存储器阵列，备用存储器阵列和重新配置存储器阵列中的任何两个，或者该装置可以适于测试所有三个存储器阵列。存储器测试硬件可以包括用于产生控制信号的控制器，耦合到控制器的用于产生数据信号的数据发生器，以及耦合到控制器的用于产生地址信号的地址发生器。测试设备还可以包括用于从主存储器阵列和备用存储器阵列接收信号并用于检测那些阵列中的故障的输出数据评估器和修复单元。

5. 发明授权

US4795920A Method and apparatus for sourcing and sinking current 失效
标题翻译：用于采集和吸收电流的方法和装置
公开(公告)号：US4795920A
公开(公告)日：1989-01-03
申请号：US79575
申请日：1987-08-03
申请人： Charles D. Hechtman , Ilyoung Kim
发明人： Charles D. Hechtman , Ilyoung Kim
IPC分类号： G05F3/24 , H03F3/45 , H03K17/687 , H03K3/353
CPC分类号： H03K17/6871 , H03F3/45381
摘要： A driver circuit for alternately sourcing current to, and sinking current from a load (12) comprises a pair of field effect transistors (20 and 22), each having its drain-to-source portion coupled between the load and a separate one of a pair of voltage sources (V.sub.H and V.sub.L) which serve to source and sink current, respectively. Each of a second pair of field effect transistors (24 and 26) has its drain-to-source portion coupled between the gate of a separate one of the first pair of field effect transistors and a current source (28). The gate of each of the field effect transistors of the second pair is supplied with a separate one of a pair of electrical signals V.sub.i ' and V.sub.i '* which alternately shift in amplitude. The control signals V.sub.i ' and V.sub.i '* render the field effect transistors of the second pair alternately nonconductive, thereby rendering the first pair of field effect transistors (20 and 22) alternately conductive to sink and source current, respectively.
摘要翻译：用于交替地将来自负载（12）的电流引入电流的驱动器电路包括一对场效应晶体管（20和22），每个场效应晶体管的漏极到源极部分耦合在负载和单独的一个一对电压源（VH和VL）分别用于源和吸收电流。第二对场效应晶体管（24和26）中的每一个具有耦合在第一对场效应晶体管中的单独一个的栅极与电流源（28）之间的漏极到源极部分。第二对的场效应晶体管的栅极被提供有交替地在振幅上移动的一对电信号Vi'和Vi'*中的单独的一个。控制信号Vi'和Vi'*使得第二对的场效应晶体管交替不导电，从而使第一对场效应晶体管（20和22）分别交替导通以吸收和源极电流。

6. 发明申请

US20080016418A1 GENERALIZED BIST FOR MULTIPORT MEMORIES 有权
标题翻译：多媒体记忆的通用单词
公开(公告)号：US20080016418A1
公开(公告)日：2008-01-17
申请号：US11775956
申请日：2007-07-11
申请人： Donald Evans , Ilyoung Kim
发明人： Donald Evans , Ilyoung Kim
IPC分类号： G11C29/00
CPC分类号： G11C29/1201 , G11C8/16 , G11C29/12 , G11C29/48
摘要： A generalized hardware architecture that supports built-in self testing (BIST) for a range of different computer memory configurations and a generalized BIST algorithm can be compiled, based on specified configuration characteristics (e.g., the number of write ports, the number of read ports, the number of entries, and the number of bits per entry in the computer memory), to generate the hardware design for a particular computer memory system. In one embodiment, the generalized hardware architecture includes a multiplexer block that enables a single BIST comparator to be multiplexed for use in performing BIST testing via different read ports of the computer memory.
摘要翻译：可以根据指定的配置特性（例如，写入端口数量，读取端口数量）编译支持内置自检（BIST）的广泛的不同计算机内存配置和广义BIST算法的通用硬件体系结构，条目数，以及计算机存储器中每个条目的位数），以产生特定计算机存储器系统的硬件设计。在一个实施例中，广义硬件架构包括多路复用器块，其使单个BIST比较器能够被复用以用于通过计算机存储器的不同读取端口执行BIST测试。

7. 发明授权

US06237123B1 Built-in self-test controlled by a token network and method 失效
标题翻译：由令牌网络和方法控制的内置自检
公开(公告)号：US06237123B1
公开(公告)日：2001-05-22
申请号：US08944618
申请日：1997-10-07
申请人： Ilyoung Kim , Paul William Rutkowski , Yervant Zorian
发明人： Ilyoung Kim , Paul William Rutkowski , Yervant Zorian
IPC分类号： G06F1100
CPC分类号： G11C29/16 , G01R31/31707 , G06F11/267 , G11C2029/0401
摘要： This invention relates to a token passing network, called a Universal BIST Scheduler (UBS), and a method for scheduling BISTed memory elements based on: executing BIST in multiple stages in order to optimize the efficiency of continuous processing and to apply a single waiting period to multiple SBRIC_RSs where, for example, BIST includes retention testing; dividing resource controllers or SBRIC_RSs corresponding to one or more RSB elements into a matrix such that each SBRIC_RS executes the BIST of its memory elements concurrently and/or successively depending on the SBRIC_RS's position in the matrix; and passing a token to initiate processing of a set of SBRIC_RSs in the matrix through a level signal rather than a pulse signal in order to ensure that the signal is not lost.
摘要翻译：本发明涉及一种称为通用BIST调度器（UBS）的令牌传递网络，以及一种用于调度BISTed存储器元件的方法，该方法基于：多级执行BIST，以便优化连续处理的效率并应用一个等待周期到多个SBRIC_RS，其中例如BIST包括保留测试; 将与一个或多个RSB元素相对应的资源控制器或SBRIC_RS分成矩阵，使得每个SBRIC_RS根据SBRIC_RS在矩阵中的位置同时和/或连续地执行其存储元件的BIST; 并通过一个令牌来通过一个电平信号而不是一个脉冲信号来处理矩阵中的一组SBRIC_RS，以确保信号不会丢失。

8. 发明授权

US5420870A Non-fully-decoded test address generator 失效
标题翻译：非完全解码的测试地址生成器
公开(公告)号：US5420870A
公开(公告)日：1995-05-30
申请号：US322462
申请日：1994-10-11
申请人： Ilyoung Kim
发明人： Ilyoung Kim
IPC分类号： H03K23/00 , G01R31/3181 , G11C8/04 , G11C29/20 , G11C29/00
CPC分类号： G01R31/31813 , G11C29/20 , G11C8/04 , G06F2201/88
摘要： An address count which increases up to, or decreases down from, a user-selected value is generated by a non-fully-decoded address generator (10) which is configured of a plurality of interconnected, sequentially-actuated of bit generators (12'.sub.1 -12'.sub.k), each generating a separate one of the bits of the address count. Each of the bit generators is presettable to at least one logic state, with at least one bit generator being presettable to a separate one of two logic states. A control circuit (30' presets the bit generators in accordance to the user-selected initial value so that when the bit generators are sequentially actuated, their collective count runs up to, or down from, the seed value.
摘要翻译：由用户选择的值增加到或降低的地址计数由非完全解码的地址发生器（10）产生，该非完全解码的地址发生器（10）由多个互连的顺序驱动的位发生器（12'）构成， 1-12'k），每个产生地址计数的位的单独一个。位发生器中的每一个被预置为至少一个逻辑状态，其中至少一个位发生器可预置为两个逻辑状态中的单独一个。控制电路（30'）根据用户选择的初始值来预设位发生器，使得当位发生器被顺序地启动时，它们的集合计数运行到种子值或者低于种子值。

9. 发明授权

US5040228A Method and apparatus for automatically focusing an image-acquisition device 失效
标题翻译：用于自动对焦图像采集装置的方法和装置
公开(公告)号：US5040228A
公开(公告)日：1991-08-13
申请号：US398876
申请日：1989-08-28
申请人： Chinmoy B. Bose , Ilyoung Kim
发明人： Chinmoy B. Bose , Ilyoung Kim
IPC分类号： G03B13/36 , G02B7/28 , G02B7/36 , H04N5/232
CPC分类号： H04N5/23212
摘要： Autofocusing of a lens (18) on a television camera (12) is achieved by first processing the image captured by the camera to establish a histogram of the intensity gradients for each of a plurality of small areas (pixels) in the captured image. From the histogram of the pixel intensity gradients, a focus index value, indicative of the sharpness of focus of the captured image, is established. The just-computed focus index value is then compared to the previously established value which is initially set to zero. The difference between the just- established and previously established focus index values establishes the direction in which the lens is incrementally stepped to more sharply focus the image. The steps of (a) capturing the image, (b) establishing the intensity gradient histogram, (c) comparing focus index value to the previously established value, and (d) incrementally stepping the lens are repeated as long as the just-established focus index values exceeds the previous value. Once the focus index value no longer exceeds the previously established value, the lens is stepped by an amount dependent on the just-established and previously established focus index values to sharply focus the image.
摘要翻译：透镜（18）在电视摄像机（12）上的自动对焦是通过首先处理由照相机拍摄的图像来建立拍摄图像中的多个小区域（像素）中的每一个的强度梯度的直方图来实现的。从像素强度梯度的直方图中，建立指示捕获图像的焦点清晰度的焦点指标值。然后将刚刚计算的焦点指数值与初始设置为零的先前建立的值进行比较。刚刚建立的和以前建立的焦点指数值之间的差异建立了透镜逐步加强的方向，以更加锐利地对焦图像。（a）拍摄图像的步骤，（b）建立强度梯度直方图，（c）将焦点指数值与先前建立的值进行比较，以及（d）逐渐地步进透镜的步骤，只要刚好确定的焦点索引值超过以前的值。一旦焦点指标值不再超过先前确定的值，则透镜按照刚刚确定的和先前建立的焦点指标值的量进行分级，以使图像锐化。

10. 发明授权

US08201032B2 Generalized BIST for multiport memories 有权
标题翻译：广播BIST多端口记忆
公开(公告)号：US08201032B2
公开(公告)日：2012-06-12
申请号：US11775956
申请日：2007-07-11
申请人： Donald A. Evans , Ilyoung Kim
发明人： Donald A. Evans , Ilyoung Kim
IPC分类号： G11C29/00 , G01R31/28 , G06F7/02 , G06F17/50
CPC分类号： G11C29/1201 , G11C8/16 , G11C29/12 , G11C29/48
摘要： A generalized hardware architecture that supports built-in self testing (BIST) for a range of different computer memory configurations and a generalized BIST algorithm can be compiled, based on specified configuration characteristics (e.g., the number of write ports, the number of read ports, the number of entries, and the number of bits per entry in the computer memory), to generate the hardware design for a particular computer memory system. In one embodiment, the generalized hardware architecture includes a multiplexer block that enables a single BIST comparator to be multiplexed for use in performing BIST testing via different read ports of the computer memory.
摘要翻译：可以根据指定的配置特性（例如，写入端口数量，读取端口数量）编译支持内置自检（BIST）的广泛的不同计算机内存配置和广义BIST算法的通用硬件体系结构，条目数，以及计算机存储器中每个条目的位数），以生成特定计算机存储器系统的硬件设计。在一个实施例中，广义硬件架构包括多路复用器块，其使单个BIST比较器能够被复用以用于通过计算机存储器的不同读取端口执行BIST测试。

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