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1. 发明申请

WO2006085326A3 SYSTEM AND METHOD FOR MITIGATING MEMORY REQUIREMENTS 审中-公开
公开(公告)号：WO2006085326A3
公开(公告)日：2006-08-17
申请号：PCT/IL2006/000179
申请日：2006-02-12
申请人： SIANO MOBILE SILICON LTD. , JASHEK, Ronen , OREN, Roy , IRONI, Alon , MEIRI, Dror
发明人： JASHEK, Ronen , OREN, Roy , IRONI, Alon , MEIRI, Dror
IPC分类号： G06F11/00 , G08C25/00 , H03M13/00 , H04L1/00
摘要： A receiver is provided, which is adapted to receive MPE-FEC frames and to correct erroneous sections within a received MPE-FEC frame by detecting unreliable sections and storing in an erasure list ("ESL") table compressed data that includes the base address of each detected erroneous section, together with the respective section's size. The size of the ESL table may be fixed, or it may correlate, or dynamically change according to the actual number of detected erroneous sections. The data stored in the erasure list may then be forwarded to a decoder to correct erroneous sections. The erroneous sections may be detected by using CRC, and the decoder may be a Reed-Solomon decoder. If the application data table of the MPE-FEC is error-free (or full or errors), in which case the erasure structure list is empty (or full of errors), in which case the erasure structure list is empty (or full), this means that no FEC reception and error corrections are required, because there are no sections to correct in the first case and the decoder is incapable of correcting too many sections in the second case. Therefore, the receiving circuitry, or at least the decoder, may be disabled to save battery power.

2. 发明申请

WO2006030409A3 A SYSTEM CIRCUIT AND METHOD FOR UTILIZING DIGITAL MEMORY ASSOCIATED WITH A HOST DEVICE FOR RECEIVED DATA 审中-公开
标题翻译：用于接收数据的主机设备使用数字存储器的系统电路和方法
公开(公告)号：WO2006030409A3
公开(公告)日：2007-05-18
申请号：PCT/IL2004001082
申请日：2004-11-25
申请人： SIANO MOBILE SILICON LTD , IRONI ALON , MEIRI DROR
发明人： IRONI ALON , MEIRI DROR
IPC分类号： H04N5/44 , H04N5/455
CPC分类号： H04N21/41407 , H04N5/4401 , H04N21/414 , H04N21/4435 , H04N21/4436
摘要： A system (Fig. 5) for a host device comprises a data processing (100) unit or demodulator to process or demodulate received data, and a host memory (150, 400) access unit to provide the data processing unit or demodulator access to digital memory (410) functionally associated with the host device, such that the data processing unit or demodulator may utilize the digital memory to process or demodulate received data.
摘要翻译：用于主机设备的系统（图5）包括用于处理或解调所接收数据的数据处理（100）单元或解调器，以及主机存储器（150,400）接入单元，以提供数据处理单元或解调器访问数字与主机设备功能相关的存储器（410），使得数据处理单元或解调器可利用数字存储器来处理或解调所接收的数据。

3. 发明申请

WO2006085326A2 SYSTEM AND METHOD FOR MITIGATING MEMORY REQUIREMENTS DURING MPE-FEC PROCESSING 审中-公开
标题翻译：用于在MPE-FEC处理期间缓解存储器要求的系统和方法
公开(公告)号：WO2006085326A2
公开(公告)日：2006-08-17
申请号：PCT/IL2006000179
申请日：2006-02-12
申请人： SIANO MOBILE SILICON LTD , JASHEK RONEN , OREN ROY , IRONI ALON , MEIRI DROR
发明人： JASHEK RONEN , OREN ROY , IRONI ALON , MEIRI DROR
IPC分类号： B01D63/00
CPC分类号： H04L1/0045 , H04L1/0057
摘要： A receiver is provided, which is adapted to receive MPE-FEC frames and to correct erroneous sections within a received MPE-FEC frame by detecting unreliable sections and storing in an erasure structure list ("ESL") table compressed data that includes the base address of each detected erroneous section, together with the respective section's size. The size of the ESL table may be fixed, or it may correlate, or dynamically change according, to the actual number of detected erroneous sections. The data stored in the erasure structure list may then be forwarded to a decoder to correct erroneous sections. The erroneous sections may be detected by using CRC, and the decoder may be a Reed-Solomon decoder. If the application data table of the MPE-FEC is error-free (or full of errors), in which case the erasure structure list is empty (or full), this means that no FEC reception and error corrections are required, because there are no sections to correct in the first case and the decoder is incapable of correcting too many sections in the second case. Therefore, the receiving circuitry, or at least the decoder, may be disabled to save battery power.
摘要翻译：提供接收器，其适于接收MPE-FEC帧并通过检测不可靠部分来校正接收到的MPE-FEC帧内的错误部分并将消息结构列表（“ESL”）存储在包括基地址每个检测到的错误部分，以及相应部分的大小。 ESL表的大小可以是固定的，或者它可以与检测到的错误部分的实际数量相关或动态地改变。存储在擦除结构列表中的数据然后可以被转发到解码器以校正错误的部分。可以通过使用CRC来检测错误部分，并且解码器可以是Reed-Solomon解码器。如果MPE-FEC的应用数据表是无错误的（或者是错误的），在这种情况下，擦除结构列表为空（或满），这意味着不需要FEC接收和纠错，因为有在第一种情况下没有要校正的部分，并且解码器在第二种情况下不能校正太多部分。因此，接收电路或至少解码器可被禁用以节省电池电量。

4. 发明申请

WO2006030409A2 A SYSTEM CIRCUIT AND METHOD FOR UTILIZING DIGITAL MEMORY ASSOCIATED WITH A HOST DEVICE FOR RECEIVED DATA 审中-公开
标题翻译：用于接收数据的主机设备使用数字存储器的系统电路和方法
公开(公告)号：WO2006030409A2
公开(公告)日：2006-03-23
申请号：PCT/IL2004/001082
申请日：2004-11-25
申请人： SIANO MOBILE SILICON LTD. , IRONI, Alon , MEIRI, Dror
发明人： IRONI, Alon , MEIRI, Dror
IPC分类号： G06F15/16
CPC分类号： H04N21/41407 , H04N5/4401 , H04N21/414 , H04N21/4435 , H04N21/4436
摘要： The present invention is a system, circuit and method of utilizing digital memory associated with a computing and/or communication device (e.g. mobile or handheld phone or video based communication and presentation device). According to some embodiments of the present invention, a receiver or receiver sub-system functionally associated with the computing and/or communication device (e.g. a data receiving circuit, sub-system or module) may store data on a digital memory also functionally associated with the device. According to some embodiments of the present invention, the sub-system may include a receiver demodulator and may store data received from outside the device, either in a processed or in an unprocessed state, where the term processed may include functions like demodulated, decoded, error detected and/or error corrected. According to some embodiments of the present invention, preprocessed data stored by the sub-system on the digital memory may be read back by the sub-system and processed.
摘要翻译：本发明是利用与计算和/或通信设备（例如移动或手持电话或基于视频的通信和呈现设备）相关联的数字存储器的系统，电路和方法。根据本发明的一些实施例，与计算和/或通信设备（例如，数据接收电路，子系统或模块）功能相关联的接收器或接收器子系统可以将数据存储在数字存储器上，该数字存储器也在功能上与装置。根据本发明的一些实施例，子系统可以包括接收机解调器，并且可以存储从设备外部接收到的数据，处理或未处理状态，其中所处理的项可以包括诸如解调，解码，检测到错误和/或纠错。根据本发明的一些实施例，由子系统存储在数字存储器上的预处理数据可以由子系统读回并进行处理。

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