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1. 发明授权

US07457897B1 PCI express-compatible controller and interface for flash memory 失效
标题翻译： PCI Express兼容控制器和闪存接口
公开(公告)号：US07457897B1
公开(公告)日：2008-11-25
申请号：US10803597
申请日：2004-03-17
申请人： Charles C. Lee , Sun-Teck See , Horng-Yee Chou , I-Pieng Peter Kao
发明人： Charles C. Lee , Sun-Teck See , Horng-Yee Chou , I-Pieng Peter Kao
IPC分类号： G06F3/00 , G06F12/00 , G06F13/00
CPC分类号： G06F13/1684 , G11C13/0004 , G11C16/102 , G11C2216/30
摘要： A PCI Express-compatible flash device can include one or more flash memory modules, a controller, and an ExpressCard interface. The controller can advantageously provide PCI Express functionality as well as flash memory operations, e.g. writing, reading, or erasing, using the ExpressCard interface. A PIO interface includes sending first and second memory request packets to the flash device. The first memory request packet includes a command word setting that prepares the flash device for the desired operation. The second memory request packet triggers the operation and includes a data payload, if needed. A DMA interface includes sending the second memory request from the flash device to the host, thereby triggering the host to release the system bus for the DMA operation.
摘要翻译：兼容PCI Express的闪存设备可以包括一个或多个闪存模块，控制器和ExpressCard接口。控制器可以有利地提供PCI Express功能以及闪速存储器操作，例如，使用ExpressCard接口进行写入，读取或擦除。 PIO接口包括向闪存设备发送第一和第二存储器请求包。第一存储器请求分组包括为所需操作准备闪存设备的命令字设置。如果需要，第二存储器请求分组触发操作并且包括数据有效载荷。 DMA接口包括将第二存储器请求从闪存设备发送到主机，从而触发主机释放用于DMA操作的系统总线。

2. 发明授权

US08306125B2 2-bin parallel decoder for advanced video processing 有权
标题翻译： 2-bin并行解码器，用于高级视频处理
公开(公告)号：US08306125B2
公开(公告)日：2012-11-06
申请号：US11755698
申请日：2007-05-30
申请人： I-pieng Peter Kao , Jack Benkual
发明人： I-pieng Peter Kao , Jack Benkual
IPC分类号： H04N11/02 , H03M7/00
CPC分类号： H04N19/436 , H04N19/91
摘要： A critical phase of video processing is the decoding of bit streams coming from standard based heavy compressed sources. Entropy coding can be effectively decoded by adopting parallelism to speed up the process. Reasonable assumptions make possible for example the multiple bits at a time processing for the Context-based Adaptive Binary Arithmetic Coding (CABAC) algorithm. In particular, a clever arithmetic section reduces single propagation for the timing critical path while decoding done for only two sequence elements at a time by calculating and maintaining most probable bit values. This in turn making accelerated path using pre-determined probability outcome through parallelism not cost.
摘要翻译：视频处理的关键阶段是对基于标准的重压缩源的比特流的解码。熵编码可以通过并行加速来有效地进行解码。合理的假设使得例如在基于上下文的自适应二进制算术编码（CABAC）算法的时间处理中的多个比特成为可能。特别地，巧妙的算术部分通过计算和维持最可能的位值，减少了时序关键路径的单次传播，同时仅对两个序列元素进行解码。这反过来使通过并行性使用预定概率结果的加速路径不是成本。

3. 发明申请

US20090049222A1 PCI Express-Compatible Controller And Interface For Flash Memory 有权
标题翻译：适用于闪存的PCI Express兼容控制器和接口
公开(公告)号：US20090049222A1
公开(公告)日：2009-02-19
申请号：US12254428
申请日：2008-10-20
申请人： Charles C. Lee , Sun-Teck See , Horng-Yee Chou , I-pieng Peter Kao
发明人： Charles C. Lee , Sun-Teck See , Horng-Yee Chou , I-pieng Peter Kao
IPC分类号： G06F13/00 , G06F12/00
CPC分类号： G06F13/1684 , G11C13/0004 , G11C16/102 , G11C2216/30
摘要： A PCI Express-compatible flash device can include one or more flash memory modules, a controller, and an ExpressCard interface. The controller can advantageously provide PCI Express functionality as well as flash memory operations, e.g. writing, reading, or erasing, using the ExpressCard interface. A PIO interface includes sending first and second memory request packets to the flash device. The first memory request packet includes a command word setting that prepares the flash device for the desired operation. The second memory request packet triggers the operation and includes a data payload, if needed. A DMA interface includes sending the second memory request from the flash device to the host, thereby triggering the host to release the system bus for the DMA operation.
摘要翻译：兼容PCI Express的闪存设备可以包括一个或多个闪存模块，控制器和ExpressCard接口。控制器可以有利地提供PCI Express功能以及闪速存储器操作，例如，使用ExpressCard接口进行写入，读取或擦除。 PIO接口包括向闪存设备发送第一和第二存储器请求包。第一存储器请求分组包括为所需操作准备闪存设备的命令字设置。如果需要，第二存储器请求分组触发操作并且包括数据有效载荷。 DMA接口包括将第二存储器请求从闪存设备发送到主机，从而触发主机释放用于DMA操作的系统总线。

4. 发明授权

US07299347B1 Boot management in computer systems assisted by an endpoint with PCI-XP or USB-V2 interface 失效
标题翻译：由PCI-XP或USB-V2接口的端点辅助的计算机系统启动管理
公开(公告)号：US07299347B1
公开(公告)日：2007-11-20
申请号：US10817601
申请日：2004-04-02
申请人： I-pieng Peter Kao
发明人： I-pieng Peter Kao
IPC分类号： G06F15/177 , G06F3/00
CPC分类号： G06F9/4401
摘要： An intelligent endpoint can provide an automated, centralized boot management for multiple, interconnected computer systems. The intelligent endpoint can be notified of a boot event for one of the computer systems. This notification can occur over a system bus or via a system fabric. The intelligent endpoint can then decide on an appropriate action for the boot event. Notably, the action may affect or depend on a boot of another computer system. The intelligent endpoint can advantageously resolve arbitration issues in a cost- and size-efficient manner. Moreover, the intelligent endpoint can provide significant flexibility during booting.
摘要翻译：智能端点可以为多个互连的计算机系统提供自动化的集中式引导管理。智能端点可以被通知一个计算机系统的引导事件。该通知可以通过系统总线或通过系统结构进行。然后，智能端点可以决定引导事件的适当操作。值得注意的是，该动作可能会影响或依赖于其他计算机系统的启动。智能端点可以有利地以成本和尺寸有效的方式解决仲裁问题。此外，智能端点可以在引导期间提供显着的灵活性。

5. 发明授权

US07849242B2 PCI express-compatible controller and interface that provides PCI express functionality and flash memory operations to host device 有权
标题翻译： PCI Express兼容控制器和接口，为主机设备提供PCI Express功能和闪存操作
公开(公告)号：US07849242B2
公开(公告)日：2010-12-07
申请号：US12254428
申请日：2008-10-20
申请人： Charles C. Lee , Sun-Teck See , Horng-Yee Chou , I-pieng Peter Kao
发明人： Charles C. Lee , Sun-Teck See , Horng-Yee Chou , I-pieng Peter Kao
IPC分类号： G06F3/00 , G06F12/00 , G06F13/00
CPC分类号： G06F13/1684 , G11C13/0004 , G11C16/102 , G11C2216/30
摘要： A PCI Express-compatible flash device can include one or more flash memory modules, a controller, and an ExpressCard interface. The controller can advantageously provide PCI Express functionality as well as flash memory operations, e.g. writing, reading, or erasing, using the ExpressCard interface. A PIO interface includes sending first and second memory request packets to the flash device. The first memory request packet includes a command word setting that prepares the flash device for the desired operation. The second memory request packet triggers the operation and includes a data payload, if needed. A DMA interface includes sending the second memory request from the flash device to the host, thereby triggering the host to release the system bus for the DMA operation.
摘要翻译：兼容PCI Express的闪存设备可以包括一个或多个闪存模块，控制器和ExpressCard接口。控制器可以有利地提供PCI Express功能以及闪速存储器操作，例如，使用ExpressCard接口进行写入，读取或擦除。 PIO接口包括向闪存设备发送第一和第二存储器请求包。第一存储器请求分组包括为所需操作准备闪存设备的命令字设置。如果需要，第二存储器请求分组触发操作并且包括数据有效载荷。 DMA接口包括将第二存储器请求从闪存设备发送到主机，从而触发主机释放用于DMA操作的系统总线。

6. 发明申请

US20090196355A1 2-BIN PARALLEL DECODER FOR ADVANCED VIDEO PROCESSING 有权
标题翻译：用于高级视频处理的2-BIN并行解码器
公开(公告)号：US20090196355A1
公开(公告)日：2009-08-06
申请号：US11755698
申请日：2007-05-30
申请人： I-pieng Peter KAO , Jack BENKUAL
发明人： I-pieng Peter KAO , Jack BENKUAL
IPC分类号： H04N11/02
CPC分类号： H04N19/436 , H04N19/91
摘要： A critical phase of video processing is the decoding of bit streams coming from standard based heavy compressed sources. Entropy coding can be effectively decoded by adopting parallelism to speed up the process. Reasonable assumptions make possible for example the multiple bits at a time processing for the Context-based Adaptive Binary Arithmetic Coding (CABAC) algorithm. In particular, a clever arithmetic section reduces single propagation for the timing critical path while decoding done for only two sequence elements at a time by calculating and maintaining most probable bit values. This in turn making accelerated path using pre-determined probability outcome through parallelism not cost.
摘要翻译：视频处理的关键阶段是对基于标准的重压缩源的比特流的解码。熵编码可以通过并行加速来有效地进行解码。合理的假设使得例如在基于上下文的自适应二进制算术编码（CABAC）算法的时间处理中的多个比特成为可能。特别地，巧妙的算术部分通过计算和维持最可能的位值，减少了时序关键路径的单次传播，同时仅对两个序列元素进行解码。这反过来使通过并行性使用预定概率结果的加速路径不是成本。

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