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1. 发明授权

US08671383B2 Viewing and debugging HDL designs having SystemVerilog interface constructs 有权
标题翻译：查看和调试具有SystemVerilog界面结构的HDL设计
公开(公告)号：US08671383B2
公开(公告)日：2014-03-11
申请号：US13443523
申请日：2012-04-10
申请人： Chih-Neng Hsu , I-Liang Ling , Qi Guo
发明人： Chih-Neng Hsu , I-Liang Ling , Qi Guo
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： Methods and systems for viewing and debugging HDL designs having SystemVerilog interface constructs are provided. An HDL design code is received, wherein the design code comprises a first module, a second module and a SystemVerilog interface construct. A first object corresponding to the first module, a second object corresponding to the second module and an interface object corresponding to the interface construct are displayed in a schematic view. The interface object is disposed between the first and second objects, and a shape of the interface object is different from that of the first and second objects. The interface signals from the first object to the second object and the interface signals from the second object to the first object pass through the interface object.
摘要翻译：提供了用于查看和调试具有SystemVerilog接口结构的HDL设计的方法和系统。接收HDL设计代码，其中设计代码包括第一模块，第二模块和SystemVerilog接口结构。对应于第一模块的第一对象，对应于第二模块的第二对象和对应于接口结构的接口对象以示意图的方式显示。接口对象设置在第一和第二对象之间，并且接口对象的形状与第一和第二对象的形状不同。接口信号从第一个对象到第二个对象，从第二个对象到第一个对象的接口信号通过接口对象。

2. 发明申请

US20130047134A1 VIEWING AND DEBUGGING HDL DESIGNS HAVING SYSTEMVERILOG INTERFACE CONSTRUCTS 有权
标题翻译：查看和调试具有系统界面结构的HDL设计
公开(公告)号：US20130047134A1
公开(公告)日：2013-02-21
申请号：US13443523
申请日：2012-04-10
申请人： Chih-Neng HSU , I-Liang LING , Qi GUO
发明人： Chih-Neng HSU , I-Liang LING , Qi GUO
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： Methods and systems for viewing and debugging HDL designs having SystemVerilog interface constructs are provided. An HDL design code is received, wherein the design code comprises a first module, a second module and a SystemVerilog interface construct. A first object corresponding to the first module, a second object corresponding to the second module and an interface object corresponding to the interface construct are displayed in a schematic view. The interface object is disposed between the first and second objects, and a shape of the interface object is different from that of the first and second objects. The interface signals from the first object to the second object and the interface signals from the second object to the first object pass through the interface object.
摘要翻译：提供了用于查看和调试具有SystemVerilog接口结构的HDL设计的方法和系统。接收HDL设计代码，其中设计代码包括第一模块，第二模块和SystemVerilog接口结构。对应于第一模块的第一对象，对应于第二模块的第二对象和对应于接口结构的接口对象以示意图的方式显示。接口对象设置在第一和第二对象之间，并且接口对象的形状与第一和第二对象的形状不同。接口信号从第一个对象到第二个对象，从第二个对象到第一个对象的接口信号通过接口对象。

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