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1. 发明申请

US20120081159A1 METHOD USING DIGITAL PHASE-LOCKED LOOP CIRCUIT INCLUDING A PHASE DELAY QUANTIZER 有权
标题翻译：使用数字相位锁定环路的方法，包括一个相位延迟量子
公开(公告)号：US20120081159A1
公开(公告)日：2012-04-05
申请号：US13323448
申请日：2011-12-12
申请人： I-chang WU
发明人： I-chang WU
IPC分类号： H03L7/06
CPC分类号： H03L7/085 , H03L7/0802 , H03L2207/50
摘要： A phase locked loop circuit and method for use, in accordance with an embodiment, implements a digital phase delay quantizer to replace the analog charge-pump and phase frequency detector in an analog PLL circuit. Therefore, the built-in loop filter can be a compact-sized, high order, high bandwidth, and high attenuation digital filter as well. The digital PLL circuit takes advantage of the deep sub-micron process technology which features high speed, high resolution, compact size, and low power.
摘要翻译：根据实施例的锁相环电路和方法用于实现数字相位延迟量化器以替代模拟PLL电路中的模拟电荷泵和相位频率检测器。因此，内置环路滤波器也可以是紧凑型，高阶，高带宽和高衰减的数字滤波器。数字PLL电路利用了深亚微米工艺技术，具有高速度，高分辨率，紧凑的尺寸和低功耗。

2. 发明授权

US08022740B2 Fast-response phase-locked loop charge-pump driven by low voltage input 有权
标题翻译：由低电压输入驱动的快速响应锁相环电荷泵
公开(公告)号：US08022740B2
公开(公告)日：2011-09-20
申请号：US12718935
申请日：2010-03-05
申请人： I-chang Wu , Chungwen Lo , Keng Leong Fong
发明人： I-chang Wu , Chungwen Lo , Keng Leong Fong
IPC分类号： H03L7/06
CPC分类号： H03L7/0896
摘要： Phase-locked loop charge pump driven by low voltage input. In one aspect, a phase-locked loop circuit includes a phase frequency detector operating at a low voltage and providing low-voltage sourcing control signals and low-voltage sinking control signals at the low voltage. A charge pump operates at a high voltage and includes a sourcing control circuit coupled to the low-voltage sourcing control signals and selectively causing the charge pump to source the sourcing current to an output of the charge pump based on the low-voltage sourcing control signals. The charge pump also includes a sinking control circuit that receives the low-voltage sinking control signals and selectively causes the charge pump to sink the sinking current from the output of the charge pump based on the low-voltage sinking control signals.
摘要翻译：锁相环电荷泵由低电压输入驱动。一方面，锁相环电路包括在低电压下工作的相位频率检测器，并在低电压下提供低电压源控制信号和低电压吸收控制信号。电荷泵以高电压工作，并且包括耦合到低电压源控制信号的源极控制电路，并且基于低电压源控制信号选择性地使电荷泵将源电流源源于电荷泵的输出。电荷泵还包括一个吸收控制电路，其接收低电压吸收控制信号，并且基于低压吸收控制信号选择性地使电荷泵从电荷泵的输出吸收吸收电流。

3. 发明授权

US06423175B1 Apparatus and method for reducing particle contamination in an etcher 有权
标题翻译：用于减少蚀刻器中颗粒污染的装置和方法
公开(公告)号：US06423175B1
公开(公告)日：2002-07-23
申请号：US09413654
申请日：1999-10-06
申请人： Yu Chih Huang , Cherng Chang Tsuei , I Chang Wu
发明人： Yu Chih Huang , Cherng Chang Tsuei , I Chang Wu
IPC分类号： C23F102
CPC分类号： H01L21/67069 , H01J37/32642 , H01J2237/022
摘要： An apparatus and a method for reducing particle contamination by a polymeric film in a plasma etcher are described. In the apparatus for dry etching a wafer, a wafer holder and a ring member positioned juxtaposed to the holder are provided wherein the ring member is used to confine a plasma cloud generated in the chamber cavity onto an exposed surface of the wafer. The ring member has surface areas that is substantially exposed to the chamber interior, the surface areas are roughened to a depth between about 1 &mgr;m and about 10 &mgr;m between peaks and valleys formed in the roughened surfaces by either a sand-blasting method or by a chemical etching method. When the sand-blasting method is utilized to roughen the surface of the ring member, i.e., a focus ring in a reactive ion etching apparatus, particles having a mesh size between 200 mesh and 80 mesh may be suitably used. The roughened surfaces on the focus ring improve adhesion between a polymeric film necessarily produced during the plasma etching process for sidewall passivation and the surface of the quartz focus ring such that polymer film does not flake-off to form contaminants for the wafer positioned in the etch chamber.
摘要翻译：描述了一种用于在等离子体蚀刻器中减少由聚合物膜引起的颗粒污染的装置和方法。在用于干蚀刻晶片的装置中，提供了与保持器并置的晶片保持器和环形构件，其中环构件用于将在室腔中产生的等离子体云限制在晶片的暴露表面上。环形构件具有基本上暴露于腔室内部的表面区域，表面区域通过喷砂方法或通过喷砂方法在粗糙表面形成的峰和谷之间粗糙化至约1μm和约10μm之间的深度化学蚀刻法。当使用喷砂方法来粗糙化环形构件的表面即反应离子蚀刻装置中的聚焦环时，可以适当地使用具有200目和80目之间的网格尺寸的颗粒。聚焦环上的粗糙表面提高了在用于侧壁钝化的等离子体蚀刻工艺期间必须产生的聚合物膜与石英聚焦环的表面之间的粘合性，使得聚合物膜不会剥落以形成位于蚀刻中的晶片的污染物房间。

4. 发明申请

US20100289541A1 DIGITAL PHASE-LOCKED LOOP CIRCUIT INCLUDING A PHASE DELAY QUANTIZER AND METHOD OF USE 有权
标题翻译：数字相位锁定环路，包括相位延迟量测器及使用方法
公开(公告)号：US20100289541A1
公开(公告)日：2010-11-18
申请号：US12465547
申请日：2009-05-13
申请人： I-chang WU
发明人： I-chang WU
IPC分类号： H03L7/06 , H03L7/00
CPC分类号： H03L7/085 , H03L7/0802 , H03L2207/50
摘要： A phase locked loop circuit in accordance with an embodiment implements a digital phase delay quantizer to replace the analog charge-pump and phase frequency detector in an analog PLL circuit. Therefore, the built-in loop filter can be a compact-sized, high order, high bandwidth, and high attenuation digital filter as well. The digital PLL circuit takes advantage of the deep sub-micron process technology which features high speed, high resolution, compact size, and low power.
摘要翻译：根据实施例的锁相环电路实现数字相位延迟量化器来替代模拟PLL电路中的模拟电荷泵和相位频率检测器。因此，内置环路滤波器也可以是紧凑型，高阶，高带宽和高衰减的数字滤波器。数字PLL电路利用了深亚微米工艺技术，具有高速度，高分辨率，紧凑的尺寸和低功耗。

5. 发明申请

US20060151116A1 Focus rings, apparatus in chamber, contact hole and method of forming contact hole 审中-公开
标题翻译：聚焦环，室内设备，接触孔和形成接触孔的方法
公开(公告)号：US20060151116A1
公开(公告)日：2006-07-13
申请号：US11035324
申请日：2005-01-12
申请人： I-Chang Wu
发明人： I-Chang Wu
IPC分类号： C23F1/00 , C03C25/68
CPC分类号： H01J37/32642 , C23F4/00 , H01J37/32623 , H01J2237/3342 , H01L21/67069
摘要： Focus rings, an apparatus in a chamber, a method of forming a contact hole structure and a contact hole structure are provided. The focus ring of a chamber substantially covers a part of a stage so as to prevent formation of particles on or near to an edge of the stage. Due to the application of the focus rings, build up of polymer particles on or near to the edge of the support ring can be substantially prevented.
摘要翻译：聚焦环，腔室中的装置，形成接触孔结构和接触孔结构的方法。腔室的聚焦环基本上覆盖了舞台的一部分，以防止在舞台边缘上或附近形成颗粒。由于聚焦环的应用，基本上可以防止聚合物颗粒在支撑环的边缘上或附近的积聚。

6. 发明授权

US08102195B2 Digital phase-locked loop circuit including a phase delay quantizer and method of use 有权
标题翻译：包括相位延迟量化器和使用方法的数字锁相环电路
公开(公告)号：US08102195B2
公开(公告)日：2012-01-24
申请号：US12465547
申请日：2009-05-13
申请人： I-chang Wu
发明人： I-chang Wu
IPC分类号： H03L7/06
CPC分类号： H03L7/085 , H03L7/0802 , H03L2207/50
摘要： A phase locked loop circuit in accordance with an embodiment implements a digital phase delay quantizer to replace the analog charge-pump and phase frequency detector in an analog PLL circuit. Therefore, the built-in loop filter can be a compact-sized, high order, high bandwidth, and high attenuation digital filter as well. The digital PLL circuit takes advantage of the deep sub-micron process technology which features high speed, high resolution, compact size, and low power.
摘要翻译：根据实施例的锁相环电路实现数字相位延迟量化器来替代模拟PLL电路中的模拟电荷泵和相位频率检测器。因此，内置环路滤波器也可以是紧凑型，高阶，高带宽和高衰减的数字滤波器。数字PLL电路利用了深亚微米工艺技术，具有高速度，高分辨率，紧凑的尺寸和低功耗。

7. 发明申请

US20090267662A1 FAST RESPONSE PHASE-LOCKED LOOP CHARGE-PUMP DRIVEN BY LOW VOLTAGE INPUT 有权
标题翻译：通过低电压输入驱动的快速响应相位锁定循环充电泵
公开(公告)号：US20090267662A1
公开(公告)日：2009-10-29
申请号：US12108329
申请日：2008-04-23
申请人： I-Chang WU , Chungwen LO , Keng Leong FONG
发明人： I-Chang WU , Chungwen LO , Keng Leong FONG
IPC分类号： H03L7/06
CPC分类号： H03L7/0896
摘要： Phase-locked loop charge pump driven by low voltage input. In one aspect, a charge pump for a phase-locked loop circuit includes a sourcing current transistor providing a sourcing current, wherein the sourcing current transistor is coupled to a high-voltage operating voltage supply. A sourcing control circuit uses low-voltage sourcing control signals to selectively cause the charge pump to source the sourcing current to an output of the charge pump, and a sinking control circuit uses low-voltage sinking control signals to selectively cause the charge pump to sink the sinking current from the output.
摘要翻译：锁相环电荷泵由低电压输入驱动。一方面，用于锁相环电路的电荷泵包括提供源极电流的源极电流晶体管，其中所述源极电流晶体管耦合到高压工作电压源。源控制电路使用低电压源控制信号来选择性地使电荷泵将源电流源源于电荷泵的输出，并且下沉控制电路使用低电压吸收控制信号来选择性地使电荷泵吸收来自输出的下沉电流。

8. 发明授权

US07348861B1 Method and apparatus for a crystal oscillator to achieve fast start-up time, low power and frequency calibration 有权
标题翻译：用于晶体振荡器的方法和装置，以实现快速启动时间，低功率和频率校准
公开(公告)号：US07348861B1
公开(公告)日：2008-03-25
申请号：US11095630
申请日：2005-03-31
申请人： I-chang Wu , Chung Wen Lo , Keng Leong Fong
发明人： I-chang Wu , Chung Wen Lo , Keng Leong Fong
IPC分类号： H03B5/32 , H03L5/00
CPC分类号： H03B5/366 , H03L3/00
摘要： One embodiment of the present invention includes a frequency generation circuit including a control module, an oscillator circuit coupled to the control module, the oscillator circuit having a start-up time defined by the time required to reach a desired frequency. The oscillator circuit includes an amplifier having an input and an output and being programmably-alterable by the control module, a first capacitor coupled to the input of the amplifier and being programmably-alterable, in capacitance, by the control module, a second capacitor coupled to the output of the amplifier, a crystal resonator coupled to the first and second capacitors for generating an output signal having a desired frequency, wherein fast start-up time is achieved.
摘要翻译：本发明的一个实施例包括频率产生电路，其包括控制模块，耦合到控制模块的振荡器电路，振荡器电路具有由达到期望频率所需的时间所限定的启动时间。振荡器电路包括具有输入和输出的放大器，并且可由控制模块编程地改变;第一电容器，耦合到放大器的输入端，并且可由控制模块以电容方式可编程地改变第二电容器耦合耦合到放大器的输出，耦合到第一和第二电容器的晶体谐振器，用于产生具有期望频率的输出信号，其中实现了快速启动时间。

9. 发明授权

US08373467B2 Method using digital phase-locked loop circuit including a phase delay quantizer 有权
标题翻译：使用包括相位延迟量化器的数字锁相环电路的方法
公开(公告)号：US08373467B2
公开(公告)日：2013-02-12
申请号：US13323448
申请日：2011-12-12
申请人： I-chang Wu
发明人： I-chang Wu
IPC分类号： H03L7/06
CPC分类号： H03L7/085 , H03L7/0802 , H03L2207/50
摘要： A phase locked loop circuit and method for use, in accordance with an embodiment, implements a digital phase delay quantizer to replace the analog charge-pump and phase frequency detector in an analog PLL circuit. Therefore, the built-in loop filter can be a compact-sized, high order, high bandwidth, and high attenuation digital filter as well. The digital PLL circuit takes advantage of the deep sub-micron process technology which features high speed, high resolution, compact size, and low power.
摘要翻译：根据实施例的锁相环电路和方法用于实现数字相位延迟量化器以替代模拟PLL电路中的模拟电荷泵和相位频率检测器。因此，内置环路滤波器也可以是紧凑型，高阶，高带宽和高衰减的数字滤波器。数字PLL电路利用了深亚微米工艺技术，具有高速度，高分辨率，紧凑的尺寸和低功耗。

10. 发明申请

US20100156484A1 FAST-RESPONSE PHASE-LOCKED LOOP CHARGE-PUMP DRIVEN BY LOW VOLTAGE INPUT 有权
标题翻译：通过低电压输入驱动的快速响应相位锁定循环充电泵
公开(公告)号：US20100156484A1
公开(公告)日：2010-06-24
申请号：US12718935
申请日：2010-03-05
申请人： I-chang WU , Chungwen LO , Keng Leong FONG
发明人： I-chang WU , Chungwen LO , Keng Leong FONG
IPC分类号： H03L7/06
CPC分类号： H03L7/0896
摘要： Phase-locked loop charge pump driven by low voltage input. In one aspect, a phase-locked loop circuit includes a phase frequency detector operating at a low voltage and providing low-voltage sourcing control signals and low-voltage sinking control signals at the low voltage. A charge pump operates at a high voltage and includes a sourcing control circuit coupled to the low-voltage sourcing control signals and selectively causing the charge pump to source the sourcing current to an output of the charge pump based on the low-voltage sourcing control signals. The charge pump also includes a sinking control circuit that receives the low-voltage sinking control signals and selectively causes the charge pump to sink the sinking current from the output of the charge pump based on the low-voltage sinking control signals.
摘要翻译：锁相环电荷泵由低电压输入驱动。一方面，锁相环电路包括在低电压下工作的相位频率检测器，并在低电压下提供低电压源控制信号和低电压吸收控制信号。电荷泵以高电压工作，并且包括耦合到低电压源控制信号的源极控制电路，并且基于低电压源控制信号选择性地使电荷泵将源电流源源于电荷泵的输出。电荷泵还包括一个吸收控制电路，其接收低电压吸收控制信号，并且基于低压吸收控制信号选择性地使电荷泵从电荷泵的输出吸收吸收电流。

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