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    • 2. 发明授权
    • Apparatus and method for guaranteeing performance of packet in Ethernet system
    • 以太网系统中保证数据包性能的装置和方法
    • US07394835B2
    • 2008-07-01
    • US10858943
    • 2004-06-01
    • Ji Wook YounHyun Ha HongJong Hyun Lee
    • Ji Wook YounHyun Ha HongJong Hyun Lee
    • H04J3/04
    • H04J3/1617H04L49/351H04L49/602
    • Provided is an apparatus for guaranteeing the performance of Ethernet packets in an Ethernet system. A packet sorting unit receives the Ethernet packets, processes header information of the Ethernet packets, and sorts the Ethernet packets. A packet processing unit stores the Ethernet packets, calculates the number of the Ethernet packets, and outputs the Ethernet packets. A packet to synchronous digital hierarchy frame converting unit receives the Ethernet packets output from the packet processing unit, converts the received Ethernet packets into synchronous digital hierarchy frames, calculates the number of the converted frames, maps the frames to a virtual container group, and outputs the virtual container group. And a signal processing unit measures the performance of the Ethernet packets on the basis of the number of the Ethernet packets stored in the packet processing unit and the number of the frames, and outputs the first and second control signals.
    • 提供了一种用于保证以太网系统中以太网数据包的性能的设备。 数据包分类单元接收以太网数据包,处理以太网数据包的头信息,对以太网数据包进行排序。 分组处理单元存储以太网分组,计算以太网分组的数量,并输出以太网分组。 分组到同步数字层级帧转换单元接收从分组处理单元输出的以太网分组,将接收到的以太网分组转换成同步数字分层帧,计算转换帧数,将帧映射到虚拟容器组,并输出 虚拟容器组。 并且信号处理单元基于存储在分组处理单元中的以太网分组的数量和帧的数量来测量以太网分组的性能​​,并且输出第一和第二控制信号。
    • 6. 发明授权
    • Apparatus and method for recovering clock signal from burst mode signal
    • 从突发模式信号恢复时钟信号的装置和方法
    • US07359461B2
    • 2008-04-15
    • US10423673
    • 2003-04-24
    • Jee-Yon ChoiHyun-Ha HongHae-Geun KimJong-Hyun Lee
    • Jee-Yon ChoiHyun-Ha HongHae-Geun KimJong-Hyun Lee
    • H04L27/14
    • H03K5/135H04L7/0276
    • There are provided an apparatus and method for recovering a clock signal from a burst mode signal. A first delay delays an input data signal for half of a time period of the input data signal, and produces a first delay signal. An XOR gate adds the input data signal and the first delay signal provided from the first delay, and provides an inverted signal of the added signal. An OR gate adds an output signal of the XOR gate and a second delay signal, and provides the added signal as a recovered clock signal. A second delay delays the added signal provided from the OR gate for an integer multiple of a time period of the input data signal, and produces the second delay signal that is provided to the OR gate. The frequency of the recovered clock signal is not limited by any delay in the gate elements due to a phase transition of the input data signal occurring when every other packet is provided.
    • 提供了一种用于从突发模式信号恢复时钟信号的装置和方法。 第一延迟将输入数据信号延迟输入数据信号的一半时间周期,并产生第一延迟信号。 XOR门将从第一延迟提供的输入数据信号和第一延迟信号相加,并提供相加信号的反相信号。 或门将XOR门和第二延迟信号的输出信号相加,并将附加的信号提供为恢复的时钟信号。 第二延迟延迟从或门提供的附加信号输入数据信号的时间周期的整数倍,并产生提供给或门的第二延迟信号。 恢复的时钟信号的频率不受限于由于当提供每隔一个分组时发生的输入数据信号的相位转变而导致门单元中的任何延迟。