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1. 发明授权

US07846786B2 Method of fabricating nano-wire array 失效
标题翻译：制造纳米线阵列的方法
公开(公告)号：US07846786B2
公开(公告)日：2010-12-07
申请号：US11927881
申请日：2007-10-30
申请人： Hong Yeol Lee , Seung Eon Moon , Eun Kyoung Kim , Jong Hyurk Park , Kang Ho Park , Jong Dae Kim , Gyu Tae Kim , Jae Woo Lee , Hye Yeon Ryu , Jung Hwan Huh
发明人： Hong Yeol Lee , Seung Eon Moon , Eun Kyoung Kim , Jong Hyurk Park , Kang Ho Park , Jong Dae Kim , Gyu Tae Kim , Jae Woo Lee , Hye Yeon Ryu , Jung Hwan Huh
IPC分类号： H01L21/00 , H01L21/16 , H01L29/06 , H01L27/088
CPC分类号： H01L29/0673 , H01L21/76289 , H01L27/1225 , H01L29/0665 , H01L29/24 , H01L29/66969 , H01L29/7869 , Y10S977/762
摘要： Provided is a method of fabricating a nano-wire array, including the steps of: depositing a nano-wire solution, which contains nano-wires, on a substrate; forming a first etch region in a stripe shape on the substrate and then patterning the nano-wires; forming drain and source electrode lines parallel to each other with the patterned nano-wires interposed therebetween; forming a plurality of drain electrodes which have one end connected to the drain electrode line and contact at least one of the nano-wires, and forming a plurality of source electrodes, which have one end connected to the source electrode line and contact the nano-wires that contact the drain electrodes; forming a second etch region between pairs of the drain and source electrodes so as to prevent electrical contacts between the pairs of the drain and source electrodes; forming an insulating layer on the substrate; and forming a gate electrode between the drain and source electrodes contacting the nano-wires on the insulating layer. Accordingly, even in an unparallel structure of nano-wires to electrode lines, a large scale nano-wire array is practicable and applicable to an integrated circuit or display unit with nano-wire alignment difficulty, as well as to device applications using flexible substrates.
摘要翻译：提供一种制造纳米线阵列的方法，包括以下步骤：在衬底上沉积包含纳米线的纳米线溶液; 在衬底上形成带状的第一蚀刻区域，然后对纳米线进行构图; 形成彼此平行的漏极和源极电极线，其间插入图案化的纳米线; 形成多个漏电极，所述多个漏电极的一端连接到所述漏电极线并接触所述纳米线中的至少一个，并且形成多个源电极，所述多个源电极的一端连接到所述源电极线并接触所述纳米线，接触漏电极的电线; 在所述漏极和源极电极之间形成第二蚀刻区域，以防止所述漏极和源极电极之间的电接触; 在所述基板上形成绝缘层; 以及在与绝缘层上的纳米线接触的漏极和源电极之间形成栅电极。因此，即使在纳米线与电极线的不平行结构中，大规模的纳米线阵列也是可行的并且适用于具有纳米线对准困难的集成电路或显示单元以及使用柔性基板的器件应用。

2. 发明申请

US20080233675A1 METHOD OF FABRICATING NANO-WIRE ARRAY 失效
标题翻译：制作纳米线阵列的方法
公开(公告)号：US20080233675A1
公开(公告)日：2008-09-25
申请号：US11927881
申请日：2007-10-30
申请人： Hong Yeol Lee , Seung Eon Moon , Eun Kyoung Kim , Jong Hyurk Park , Kang Ho Park , Jong Dae Kim , Gyu Tae Kim , Jae Woo Lee , Hye Yeon Ryu , Jung Hwan Huh
发明人： Hong Yeol Lee , Seung Eon Moon , Eun Kyoung Kim , Jong Hyurk Park , Kang Ho Park , Jong Dae Kim , Gyu Tae Kim , Jae Woo Lee , Hye Yeon Ryu , Jung Hwan Huh
IPC分类号： H01L21/00
CPC分类号： H01L29/0673 , H01L21/76289 , H01L27/1225 , H01L29/0665 , H01L29/24 , H01L29/66969 , H01L29/7869 , Y10S977/762
摘要： Provided is a method of fabricating a nano-wire array, including the steps of: depositing a nano-wire solution, which contains nano-wires, on a substrate; forming a first etch region in a stripe shape on the substrate and then patterning the nano-wires; forming drain and source electrode lines parallel to each other with the patterned nano-wires interposed therebetween; forming a plurality of drain electrodes which have one end connected to the drain electrode line and contact at least one of the nano-wires, and forming a plurality of source electrodes, which have one end connected to the source electrode line and contact the nano-wires that contact the drain electrodes; forming a second etch region between pairs of the drain and source electrodes so as to prevent electrical contacts between the pairs of the drain and source electrodes; forming an insulating layer on the substrate; and forming a gate electrode between the drain and source electrodes contacting the nano-wires on the insulating layer. Accordingly, even in an unparallel structure of nano-wires to electrode lines, a large scale nano-wire array is practicable and applicable to an integrated circuit or display unit with nano-wire alignment difficulty, as well as to device applications using flexible substrates.
摘要翻译：提供一种制造纳米线阵列的方法，包括以下步骤：在衬底上沉积包含纳米线的纳米线溶液; 在衬底上形成带状的第一蚀刻区域，然后对纳米线进行构图; 形成彼此平行的漏极和源极电极线，其间插入图案化的纳米线; 形成多个漏电极，所述多个漏电极的一端连接到所述漏电极线并接触所述纳米线中的至少一个，并且形成多个源电极，所述多个源电极的一端连接到所述源电极线并接触所述纳米线，接触漏电极的电线; 在所述漏极和源极电极之间形成第二蚀刻区域，以防止所述漏极和源极电极之间的电接触; 在所述基板上形成绝缘层; 以及在与绝缘层上的纳米线接触的漏极和源电极之间形成栅电极。因此，即使在纳米线与电极线的不平行结构中，大规模的纳米线阵列也是可行的并且适用于具有纳米线对准困难的集成电路或显示单元以及使用柔性基板的器件应用。

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