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    • 6. 发明授权
    • Source follower for low voltage differential signaling
    • 源极跟随器用于低电压差分信号
    • US06552582B1
    • 2003-04-22
    • US09966388
    • 2001-09-27
    • Thomas Clark BryanHarry Huy Dang
    • Thomas Clark BryanHarry Huy Dang
    • H03B100
    • H03K19/018514H03K17/6871H04L25/0272
    • A source follower circuit for low voltage differential signaling (LVDS) has a low power consumption, low noise, and the ability to drive a highly capacitive load at an output port of an integrated circuit (IC). The source follower circuit includes a first p-channel transistor having a drain coupled to a supply voltage and a gate coupled to a first input; a second p-channel transistor having a drain coupled to the supply voltage and a gate coupled to a second input which is complementary to the first input; a third p-channel transistor having a gate coupled to the second input, a source coupled to ground, and a drain coupled to a source of the first p-channel transistor which forms a first output; and a fourth p-channel transistor having a source coupled to the ground and a drain coupled to a source of the second p-channel transistor which forms a second output which is complementary to the first output. Advantageously, the output signals of the circuit are referenced to ground and are less affected by power supply variations.
    • 用于低电压差分信号(LVDS)的源极跟随器电路具有低功耗,低噪声以及在集成电路(IC)的输出端口处驱动高容性负载的能力。 源极跟随器电路包括具有耦合到电源电压的漏极和耦合到第一输入的栅极的第一p沟道晶体管; 具有耦合到所述电源电压的漏极的第二p沟道晶体管和耦合到与所述第一输入互补的第二输入的栅极; 第三p沟道晶体管,其具有耦合到第二输入的栅极,耦合到地的源极和耦合到形成第一输出的第一p沟道晶体管的源极的漏极; 以及第四p沟道晶体管,其具有耦合到地的源极和耦合到第二p沟道晶体管的源极的漏极,其形成与第一输出互补的第二输出。 有利地,电路的输出信号参考地,并且受电源变化的影响较小。
    • 7. 发明授权
    • Complementary metal-oxide semiconductor buffer
    • 互补金属氧化物半导体缓冲液
    • US06169421A
    • 2001-01-02
    • US09303726
    • 1999-05-03
    • Thomas Clark BryanHarry Huy Dang
    • Thomas Clark BryanHarry Huy Dang
    • H03K190948
    • H03K19/0013
    • A CMOS buffer for interfacing TTL-standard signals and capable of driving a high capacitance load such as a transmission line with low switching noise and low power consumption. The CMOS buffer includes two CMOS branch circuits that control the operation of a CMOS output device. Each branch circuit includes a first delay and a second delay greater than the first delay. The CMOS output device includes a complementary pair of MOS transistors. The first MOS transistor of the CMOS output device is operated by the first branch circuit in response to a signal that is delayed by the first or the second delay. The second MOS transistor of the CMOS output device is operated by the second branch circuit in response to delay of the signal by the second or the first delay.
    • 用于连接TTL标准信号并能够驱动高电容负载的CMOS缓冲器,例如具有低开关噪声和低功耗的传输线。 CMOS缓冲器包括两个CMOS分支电路,用于控制CMOS输出设备的工作。 每个分支电路包括大于第一延迟的第一延迟和第二延迟。 CMOS输出装置包括一对互补的MOS晶体管。 CMOS输出装置的第一MOS晶体管响应于延迟了第一或第二延迟的信号由第一分支电路操作。 CMOS输出装置的第二MOS晶体管响应于第二或第一延迟的信号延迟由第二分支电路操作。