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1. 发明申请

US20080272433A1 DUAL METAL GATES FOR MUGFET DEVICE 有权
标题翻译：双金属门为MUGFET设备
公开(公告)号：US20080272433A1
公开(公告)日：2008-11-06
申请号：US11744322
申请日：2007-05-04
申请人： Husam Niman Alshareef , Weize Xiong
发明人： Husam Niman Alshareef , Weize Xiong
IPC分类号： H01L21/12 , H01L21/84
CPC分类号： H01L27/1211 , H01L21/28088 , H01L21/84 , H01L21/845 , H01L27/1203 , H01L29/4966 , H01L29/66795 , H01L29/785
摘要： Exemplary embodiments provide methods and structures for controlling work function values of dual metal gate electrodes for transistor devices. Specifically, the work function value of one of the PMOS and NMOS metal gate electrodes can be controlled by a reaction between stacked layers deposited on a gate dielectric material. The stacked layers can include a first-metal-containing material such as Al2O3, and/or AlN overlaid by a second-metal-containing material such as TaN, TiN, WN, MoN or their respective metals. The reaction between the stacked layers can create a metal gate material with a desired work function value ranging from about 4.35 eV to about 5.0 eV. The disclosed methods and structures can be used for CMOS transistors including MOSFET devices formed on a bulk substrate, and planar FET devices or 3-D MuGFET devices (e.g., FinFET devices) formed upon the oxide insulator of a SOI.
摘要翻译：示例性实施例提供了用于控制用于晶体管器件的双金属栅电极的功函数值的方法和结构。具体地，PMOS和NMOS金属栅电极之一的功函数值可以通过沉积在栅介电材料上的堆叠层之间的反应来控制。堆叠层可以包括第一含金属的材料，例如Al 2 O 3 N，和/或由包含第二金属的材料如TaN覆盖的AlN， TiN，WN，MoN或它们各自的金属。堆叠层之间的反应可产生具有约4.35eV至约5.0eV范围内的期望功函数值的金属栅极材料。公开的方法和结构可以用于包括形成在体衬底上的MOSFET器件的CMOS晶体管，以及形成在SOI的氧化物绝缘体上的平面FET器件或3-D MuGFET器件（例如，FinFET器件）。

2. 发明授权

US07582521B2 Dual metal gates for mugfet device 有权
标题翻译：双金属门用于mugfet设备
公开(公告)号：US07582521B2
公开(公告)日：2009-09-01
申请号：US11744322
申请日：2007-05-04
申请人： Husam Niman Alshareef , Weize Xiong
发明人： Husam Niman Alshareef , Weize Xiong
IPC分类号： H01L21/8238
CPC分类号： H01L27/1211 , H01L21/28088 , H01L21/84 , H01L21/845 , H01L27/1203 , H01L29/4966 , H01L29/66795 , H01L29/785
摘要： Exemplary embodiments provide methods and structures for controlling work function values of dual metal gate electrodes for transistor devices. Specifically, the work function value of one of the PMOS and NMOS metal gate electrodes can be controlled by a reaction between stacked layers deposited on a gate dielectric material. The stacked layers can include a first-metal-containing material such as Al2O3, and/or AlN overlaid by a second-metal-containing material such as TaN, TiN, WN, MoN or their respective metals. The reaction between the stacked layers can create a metal gate material with a desired work function value ranging from about 4.35 eV to about 5.0 eV. The disclosed methods and structures can be used for CMOS transistors including MOSFET devices formed on a bulk substrate, and planar FET devices or 3-D MuGFET devices (e.g., FinFET devices) formed upon the oxide insulator of a SOI.
摘要翻译：示例性实施例提供了用于控制用于晶体管器件的双金属栅电极的功函数值的方法和结构。具体地，PMOS和NMOS金属栅电极之一的功函数值可以通过沉积在栅介电材料上的层叠层之间的反应来控制。堆叠层可以包括第一金属含量的材料，例如Al 2 O 3和/或由第二金属含量的材料如TaN，TiN，WN，MoN或它们各自的金属覆盖的AlN。堆叠层之间的反应可产生具有约4.35eV至约5.0eV范围内的期望功函数值的金属栅极材料。所公开的方法和结构可以用于包括形成在体衬底上的MOSFET器件的CMOS晶体管，以及形成在SOI的氧化物绝缘体上的平面FET器件或3-D MuGFET器件（例如，FinFET器件）。

3. 发明申请

US20080237604A1 PLASMA NITRIDED GATE OXIDE, HIGH-K METAL GATE BASED CMOS DEVICE 审中-公开
标题翻译：等离子体氮化物氧化物，高K金属栅基CMOS器件
公开(公告)号：US20080237604A1
公开(公告)日：2008-10-02
申请号：US11694419
申请日：2007-03-30
申请人： Husam Niman Alshareef , Manuel Quevedo-Lopez
发明人： Husam Niman Alshareef , Manuel Quevedo-Lopez
IPC分类号： H01L27/108 , H01L21/8238
CPC分类号： H01L21/823857 , H01L21/02164 , H01L21/02181 , H01L21/02189 , H01L21/02332 , H01L21/0234 , H01L21/28194 , H01L21/28202 , H01L21/3145 , H01L21/31604 , H01L21/31616 , H01L21/31641 , H01L21/31645 , H01L21/823828 , H01L27/092 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/518
摘要： In accordance with the invention, there are CMOS devices and semiconductor devices and methods of fabricating them. The CMOS device can include a substrate including a first active region and a second active region and a first transistor device over the first active region, wherein the first transistor device includes a high-K layer over the first active region, a first dielectric capping layer on the high-K layer, and a first metal gate layer over the first dielectric capping layer. The CMOS device can also include a second transistor device over the second active region, wherein the second transistor device includes a high-K layer over the second active region, a second dielectric capping layer on the second high-K layer, and a second metal gate layer over the second dielectric capping layer.
摘要翻译：根据本发明，存在CMOS器件和半导体器件及其制造方法。 CMOS器件可以包括在第一有源区上方包括第一有源区和第二有源区的衬底和第一晶体管器件，其中第一晶体管器件包括在第一有源区上的高K层，第一介电覆盖层在高K层上，以及在第一介电覆盖层上方的第一金属栅极层。 CMOS器件还可以包括在第二有源区上的第二晶体管器件，其中第二晶体管器件包括在第二有源区上的高K层，在第二高K层上的第二介电覆盖层，以及第二金属栅极层在第二介电覆盖层上。

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