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2. 发明授权

US06479398B1 Method of manufacturing an amorphous-silicon thin film transistor 有权
标题翻译：制造非晶硅薄膜晶体管的方法
公开(公告)号：US06479398B1
公开(公告)日：2002-11-12
申请号：US09692247
申请日：2000-10-18
申请人： Jr-Hong Chen , Jeng-Hung Sun , Hsixg-Ju Sung , Pi-Fu Chen , Dou-I Chen
发明人： Jr-Hong Chen , Jeng-Hung Sun , Hsixg-Ju Sung , Pi-Fu Chen , Dou-I Chen
IPC分类号： H01L21302
CPC分类号： H01L29/66765 , H01L29/78669
摘要： A structure of an amorphous-silicon thin film transistor array comprises a substrate, a gate electrode, a gate insulating layer, an amorphous-silicon active layer, an n+ amorphous-silicon layer and a metal layer. The metal layer defines a source electrode and a drain electrode. The structure simplifies the photolithography process by using a less number of masks to manufacture thin film transistors. It also reduces the occurrence of open circuits in the first metal (MI) layer or short circuits between the MI layer and the second metal (MII) layer caused by the photoresist residue or particle contamination. The manufacturing method combines a conventional back-channel-etched (BCE) reduced mask process and a two-step exposure technology. The two-step exposure technology uses two photoresist pattern masks. One is a pattern mask for complete exposure with higher light intensity and the other is a pattern mask for incomplete exposure with lower light intensity. The photoresist pattern with incomplete exposure is then etched by an O2 plasma etching process. The amorphous-silicon layer and the metal layer has the characteristic of an island metal masking structure that protects the active layer from plasma damage in plasma etching process.
摘要翻译：非晶硅薄膜晶体管阵列的结构包括基板，栅电极，栅绝缘层，非晶硅有源层，n +非晶硅层和金属层。金属层限定了源电极和漏电极。该结构通过使用较少数量的掩模来制造薄膜晶体管来简化光刻工艺。它还减少了第一金属（MI）层中的开路的发生或由光致抗蚀剂残留物或颗粒污染引起的MI层和第二金属（MII）层之间的短路。该制造方法结合了常规的背沟道蚀刻（BCE）减少掩模工艺和两步曝光技术。两步曝光技术使用两个光刻胶图案掩模。一种是具有较高光强度的完全曝光的图案掩模，另一种是具有较低光强度的不完全曝光的图案掩模。然后通过O 2等离子体蚀刻工艺蚀刻具有不完全曝光的光致抗蚀剂图案。非晶硅层和金属层具有在等离子体蚀刻工艺中保护有源层免受等离子体损伤的岛金属掩蔽结构的特征。

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