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    • 4. 发明授权
    • Method and apparatus for noise burst detection in signal processors
    • 信号处理器中噪声突发检测的方法和装置
    • US5966406A
    • 1999-10-12
    • US815849
    • 1997-03-12
    • Chau-Kai HsiehHsin-Mei Chen
    • Chau-Kai HsiehHsin-Mei Chen
    • H04B1/10H04B3/46
    • H04B1/1027
    • A method and apparatus for noise burst detection in a signal processor is provided. The method and apparatus is based on the zero-crossing rate (ZCR) of the received signal, which is defined as the number of times the magnitude of the received signal becomes zero during a specific counting period, to determine whether the received signal is a noise or a normal signal. The received signal is sampled at a specified sampling rate. Whether the signal waveform undergoes a zero-crossing is determined by comparing the polarity of the current sampled magnitude with that of the previous one. If the polarities are different, it indicates that the signal waveform has undergone a zero-crossing during the current sampling period; otherwise, it indicates that the signal waveform has not undergone a zero-crossing. The count of zero-crossing during each counting period is compared with a preset threshold value. If the count is larger than the threshold value, it indicates the received signal is noise; otherwise, the received signal is a normal signal.
    • 提供了一种用于信号处理器中的噪声突发检测的方法和装置。 该方法和装置基于接收信号的过零率(ZCR),其被定义为在特定计数周​​期期间接收信号的幅度变为零的次数,以确定接收信号是否为 噪声或正常信号。 接收的信号以指定的采样速率进行采样。 通过将电流采样幅度的极性与前一个采样幅度的极性进行比较来确定信号波形是否经过过零。 如果极性不同,则表示信号波形在当前采样周期内经过过零; 否则表示信号波形未经过过零。 将每个计数期间的过零计数与预设的阈值进行比较。 如果计数大于阈值,则表示接收到的信号是噪声; 否则,接收到的信号是正常信号。
    • 5. 发明授权
    • DSP system for capturing data at a fixed rate
    • 用于以固定速率捕获数据的DSP系统
    • US06799281B1
    • 2004-09-28
    • US09812005
    • 2001-03-19
    • Hsin-Mei ChenChung-Ping Hsu
    • Hsin-Mei ChenChung-Ping Hsu
    • G06F112
    • G06F13/4213
    • A DSP system, capturing the data from a main bus via a bus operating at the clock speed of a first frequency, and sending the data to a DSP unit reading the data at the clock speed of a second frequency, the DSP system comprising: a bus control unit, which is adapted to transfer data from the main bus to the bus; a pulse wave generator, producing a pulse wave that synchronous to the bus, the pulse wave is comprised of sequential time slots, wherein a part of the time slots are DRQ slots that respectively comprises a data requesting signal, and the other times slots are normal slots; and an interface unit, capturing the data from the bus control unit via the bus according to the data requesting signal, and transmitting the data to the DSP unit. According to the DSP system of the present invention, the FIFO register that used in the prior art could be abandoned, whereby saving the occupied space of the whole system.
    • 一种DSP系统,通过以第一频率的时钟速度操作的总线从主总线捕获数据,并将数据发送到以第二频率的时钟速度读取数据的DSP单元,DSP系统包括: 总线控制单元,适用于将数据从主总线传输到总线; 产生与总线同步的脉搏波的脉搏波发生器,脉波由顺序时隙组成,其中一部分时隙是分别包括数据请求信号的DRQ时隙,另一时隙是正常的 槽 以及接口单元,根据数据请求信号,经由总线从总线控制单元捕获数据,并将数据发送到DSP单元。 根据本发明的DSP系统,可以放弃现有技术中使用的FIFO寄存器,从而节省整个系统的占用空间。