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1. 发明授权

US07382728B2 Networking switching apparatus and method for congestion control 有权
标题翻译：网络交换装置和拥塞控制方法
公开(公告)号：US07382728B2
公开(公告)日：2008-06-03
申请号：US10157238
申请日：2002-05-30
申请人： Jen-Kai Chen , Hsiang-Yi Huang
发明人： Jen-Kai Chen , Hsiang-Yi Huang
IPC分类号： H04L12/56
CPC分类号： H04L47/10 , H04L47/2433 , H04L47/50 , H04L47/6215
摘要： A network switching apparatus and method for congestion control. Each one of the connection ports of the switching apparatus includes a low priority queue and a high priority queue. When a data packet enters a switching apparatus, the switching apparatus according to the type of the data packet enqueues the data packet to the low priority queue or the high priority queue. When congestion occurs at the switching apparatus, the low priority queue and the high priority queue can respectively perform the different ways of the congestion control, according to the input congestion mode. Also, when the switching apparatus receives a pause frame, response flow control can be performed, according to the output congestion mode. Since the different ways of the congestion control are performed according to the different types of the data packet, the congestion control can be optimized.
摘要翻译：一种用于拥塞控制的网络交换设备和方法。交换设备的每个连接端口包括低优先级队列和高优先级队列。当数据分组进入交换设备时，根据数据分组的类型的交换设备将数据分组引入低优先级队列或高优先级队列。当交换装置发生拥塞时，根据输入拥塞模式，低优先级队列和高优先级队列可以分别执行拥塞控制的不同方式。此外，当切换装置接收到暂停帧时，可以根据输出拥塞模式执行响应流控制。由于根据不同类型的数据包执行拥塞控制的不同方式，所以可以优化拥塞控制。

2. 发明申请

US20070226529A1 Memory controller and device with data strobe calibration 有权
标题翻译：内存控制器和具有数据选通校准的设备
公开(公告)号：US20070226529A1
公开(公告)日：2007-09-27
申请号：US11385501
申请日：2006-03-21
申请人： Hsiang-Yi Huang
发明人： Hsiang-Yi Huang
IPC分类号： G06F1/12
CPC分类号： G06F5/06
摘要： A memory controller comprises a DQ path, a DQS path, a delay element, a flip flop, and an adjustment unit. The DQ path receives and passes a data signal, and outputs a delayed data signal. The DQS path receives and passes a data strobe signal. The delay element is coupled to the DQS path, receiving the data strobe signal to generate a compensated data strobe signal having a calibrated latency. The calibrated latency is determined by an adjustment signal. The flip flop is coupled to the data signal path and the delay element, sampling the delayed data signal by the compensated data strobe signal to generate an output data. The adjustment unit generates the adjustment signal according to the output data. The adjustment unit performs a calibration to adjust the adjustment signal, thus the calibrated latency is adjusted.
摘要翻译：存储器控制器包括DQ路径，DQS路径，延迟元件，触发器和调整单元。 DQ路径接收并传送数据信号，并输出延迟的数据信号。 DQS路径接收并传递数据选通信号。延迟元件耦合到DQS路径，接收数据选通信号以产生具有校准等待时间的补偿数据选通信号。校准的等待时间由调整信号确定。触发器耦合到数据信号路径和延迟元件，通过补偿的数据选通信号对延迟的数据信号进行采样以产生输出数据。调整单元根据输出数据生成调整信号。调整单元执行校准以调整调整信号，从而校准校准的等待时间。

3. 发明授权

US07310311B2 Ethernet switch with rate control and associated method 有权
标题翻译：具有速率控制和相关方法的以太网交换机
公开(公告)号：US07310311B2
公开(公告)日：2007-12-18
申请号：US10384697
申请日：2003-03-11
申请人： Jen-Kai Chen , Hsiao-Lung Wu , Hsiang-Yi Huang
发明人： Jen-Kai Chen , Hsiao-Lung Wu , Hsiang-Yi Huang
IPC分类号： G01R31/08 , H04J1/16 , H04L1/00
CPC分类号： H04L49/351 , H04L49/50
摘要： An Ethernet switch with rate control and associated method is provided. Each port in the switch has individual settings of egress/ingress) rate control, which are stored in a register and configured based on required rates. The switch uses data volume that a port can output/input within each unit time to control egress/ingress rate of the port. Further, the egress rate can be precisely controlled by using uniform random numbers provided by an random number generator of the switch, and the ingress rate can be advantageously controlled by combining a proper kind of congestion control, which is performed according to the capability of a device connected to the port, such as full-duplex or half-duplex, and flow control.
摘要翻译：提供了一种具有速率控制和相关方法的以太网交换机。交换机中的每个端口都有单独的出口/入口设置）速率控制，它们存储在寄存器中，并根据所需的速率进行配置。交换机使用端口可以在每个单位时间内输出/输入的数据量，以控制端口的出口/入口速率。此外，可以通过使用由交换机的随机数发生器提供的均匀随机数来精确地控制出口速率，并且可以有利地通过组合适当类型的拥塞控制来控制入口速率，所述拥塞控制是根据连接到端口的设备，如全双工或半双工，以及流量控制。

4. 发明授权

US10180226B1 High/low beam switching device and headlamp comprising the same 有权
公开(公告)号：US10180226B1
公开(公告)日：2019-01-15
申请号：US15823600
申请日：2017-11-28
申请人： Hsiang-Yi Huang , Hsiu-Ming Huang
发明人： Hsiang-Yi Huang , Hsiu-Ming Huang
IPC分类号： F21V1/00 , F21S41/692 , F21S41/43 , F21S41/141 , F21Y115/10
摘要： A high/low beam switching device generally includes a fixing plate, a solenoid device, a shielding member, and a coil spring. The fixing plate defines an opening which is divided into three zones including an upper space, a middle space, and a lower space. The solenoid device is horizontally disposed in a frame fixed on a shelf extending from the fixing plate. The shielding member, which can cover the middle space of the fixing plate, is pivotally connected to the fixing plate. The solenoid device when being energized can turn the shielding member to uncover the middle space, so that a high beam illumination pattern can be provided. When the solenoid device is de-energized, the shielding member can be turned back to the fixing plate to cover the middle space, so that a low beam illumination pattern can be provided. Also, the present invention provides a headlamp including the switching device.

5. 发明申请

US20100153766A1 MEMORY CONTROLLER AND DEVICE WITH DATA STROBE CALIBRATION 有权
标题翻译：存储器控制器和具有数据条纹校准的器件
公开(公告)号：US20100153766A1
公开(公告)日：2010-06-17
申请号：US12711410
申请日：2010-02-24
申请人： Hsiang-Yi Huang
发明人： Hsiang-Yi Huang
IPC分类号： G06F1/12 , G06F12/00
CPC分类号： G06F5/06
摘要： A memory controller comprises a DQ path, a DQS path, a delay element, a flip flop, and an adjustment unit. The DQ path receives and passes a data signal, and outputs a delayed data signal. The DQS path receives and passes a data strobe signal. The delay element is coupled to the DQS path, receiving the data strobe signal to generate a compensated data strobe signal having a calibrated latency. The calibrated latency is determined by an adjustment signal. The flip flop is coupled to the data signal path and the delay element, sampling the delayed data signal by the compensated data strobe signal to generate an output data. The adjustment unit generates the adjustment signal according to the output data. The adjustment unit performs a calibration to adjust the adjustment signal, thus the calibrated latency is adjusted.
摘要翻译：存储器控制器包括DQ路径，DQS路径，延迟元件，触发器和调整单元。 DQ路径接收并传送数据信号，并输出延迟的数据信号。 DQS路径接收并传递数据选通信号。延迟元件耦合到DQS路径，接收数据选通信号以产生具有校准等待时间的补偿数据选通信号。校准的等待时间由调整信号确定。触发器耦合到数据信号路径和延迟元件，通过补偿的数据选通信号对延迟的数据信号进行采样以产生输出数据。调整单元根据输出数据生成调整信号。调整单元执行校准以调整调整信号，从而校准校准的等待时间。

6. 发明授权

US07698589B2 Memory controller and device with data strobe calibration 有权
标题翻译：内存控制器和具有数据选通校准的设备
公开(公告)号：US07698589B2
公开(公告)日：2010-04-13
申请号：US11385501
申请日：2006-03-21
申请人： Hsiang-Yi Huang
发明人： Hsiang-Yi Huang
IPC分类号： G06F1/12
CPC分类号： G06F5/06
摘要： A memory controller comprises a DQ path, a DQS path, a delay element, a flip flop, and an adjustment unit. The DQ path receives and passes a data signal, and outputs a delayed data signal. The DQS path receives and passes a data strobe signal. The delay element is coupled to the DQS path, receiving the data strobe signal to generate a compensated data strobe signal having a calibrated latency. The calibrated latency is determined by an adjustment signal. The flip flop is coupled to the data signal path and the delay element, sampling the delayed data signal by the compensated data strobe signal to generate an output data. The adjustment unit generates the adjustment signal according to the output data. The adjustment unit performs a calibration to adjust the adjustment signal, thus the calibrated latency is adjusted.
摘要翻译：存储器控制器包括DQ路径，DQS路径，延迟元件，触发器和调整单元。 DQ路径接收并传送数据信号，并输出延迟的数据信号。 DQS路径接收并传递数据选通信号。延迟元件耦合到DQS路径，接收数据选通信号以产生具有校准等待时间的补偿数据选通信号。校准的等待时间由调整信号确定。触发器耦合到数据信号路径和延迟元件，通过补偿的数据选通信号对延迟的数据信号进行采样以产生输出数据。调整单元根据输出数据生成调整信号。调整单元执行校准以调整调整信号，从而校准校准的等待时间。

7. 发明授权

US07069399B2 Method and related apparatus for reordering access requests used to access main memory of a data processing system 有权
标题翻译：用于重新排序用于访问数据处理系统的主存储器的访问请求的方法和相关装置
公开(公告)号：US07069399B2
公开(公告)日：2006-06-27
申请号：US10609386
申请日：2003-07-01
申请人： Frank Lin , Victor Wu , Jacky Tsai , Hsiang-Yi Huang , Vincent Chang , Michael Liu , Heng-Chen Ho
发明人： Frank Lin , Victor Wu , Jacky Tsai , Hsiang-Yi Huang , Vincent Chang , Michael Liu , Heng-Chen Ho
IPC分类号： G06F13/00
CPC分类号： G06F13/1631
摘要： A method and related apparatus for reordering access requests used to access main memory of a data processing system. The method includes receiving one or more access requests for accessing the memory device in a first predetermined order, and reordering the access requests in a second predetermined order to be processed in a request queue by relocating a first access request to follow a second access request accessing a same memory page to increase processing efficiency. In addition, the relocating is prohibited if it increases a processing latency for a third access request to exceed a predetermined limit.
摘要翻译：一种用于重新排序用于访问数据处理系统的主存储器的访问请求的方法和相关装置。该方法包括以第一预定顺序接收访问存储器件的一个或多个访问请求，并且以第二预定顺序重新排序访问请求，以便在请求队列中处理，通过重定位第一访问请求以跟随第二访问请求访问相同的内存页面来提高处理效率。此外，如果增加第三访问请求的处理延迟超过预定限制，则禁止重新定位。

8. 发明授权

US07050059B2 Method for a graphics chip to access data stored in a system memory of a computer device 有权
标题翻译：用于图形芯片访问存储在计算机设备的系统存储器中的数据的方法
公开(公告)号：US07050059B2
公开(公告)日：2006-05-23
申请号：US10708662
申请日：2004-03-18
申请人： Frank Lin , Victor Wu , Jacky Tsai , Hsiang-Yi Huang , Vincent Chang , Michael Liu , Heng-Chen Ho
发明人： Frank Lin , Victor Wu , Jacky Tsai , Hsiang-Yi Huang , Vincent Chang , Michael Liu , Heng-Chen Ho
IPC分类号： G09G5/39 , G06F15/76
CPC分类号： G06F13/1642 , G06F3/14 , G06F13/1626
摘要： A method for a graphics chip to access data stored in a system memory of a computer device is disclosed. The method includes using a memory controller to set a block capacity value; using the memory controller to divide a plurality of read requests corresponding to a predetermined request sequence into a plurality of request groups, wherein a total amount of data required by read requests grouped in each request group is less than the block capacity value; and using the memory controller to adjust a request sequence corresponding to read requests grouped in each request group for retrieving data stored at different N pages so that a memory device only performs N−1 page switching operations.
摘要翻译：公开了一种图形芯片访问存储在计算机设备的系统存储器中的数据的方法。该方法包括使用存储器控制器来设置块容量值; 使用存储器控制器将对应于预定请求序列的多个读取请求划分为多个请求组，其中分组在每个请求组中的读取请求所需的总数据量小于块容量值; 并且使用存储器控制器来调整与分组在每个请求组中的读取请求相对应的请求序列，用于检索存储在不同N页面的数据，使得存储器设备仅执行N-1个页面切换操作。

9. 发明授权

US06704312B1 Switching apparatus and method using bandwidth decomposition 失效
标题翻译：开关装置和方法使用带宽分解
公开(公告)号：US06704312B1
公开(公告)日：2004-03-09
申请号：US09569318
申请日：2000-05-11
申请人： Cheng-Shang Chang , Wen-Jyh Chen , Hsiang-Yi Huang
发明人： Cheng-Shang Chang , Wen-Jyh Chen , Hsiang-Yi Huang
IPC分类号： H04L1228
CPC分类号： H04L47/2425 , H04L47/283 , H04L49/101 , H04L49/254 , H04L49/3018
摘要： The present invention discloses a switching apparatus and method using bandwidth decomposition, appling a von Neumann algorithm, a Birkhoff theorem, a Packetized Generalized Processor Sharing algorithm, a water filling algorithm and a dynamnically calculating rate algorithm in packet switching of a high speed network. It is not necessary to speed up internally and determine a maximal matching between input ports and output ports for the switching apparatus and method using bandwidth decomposition according to the present invention, so the executing speed of a network using the present appatatus and method will be increased, and the manufacturing of the present invention can be easily implemented by current VLSI technology.
摘要翻译：本发明公开了一种在高速网络的分组交换中使用带宽分解，应用冯诺依曼算法，Birkhoff定理，分组化广义处理器共享算法，灌水算法和动态计算速率算法的开关装置和方法。不需要在内部加速，并且根据本发明确定用于切换装置的输入端口和输出端口之间的最大匹配以及使用根据本发明的带宽分解的方法，因此使用本申请的方法的网络的执行速度将增加，并且本发明的制造可以通过目前的VLSI技术容易地实现。

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