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1. 发明授权

US07310257B2 Local digit line architecture and method for memory devices having multi-bit or low capacitance memory cells 有权
标题翻译：具有多位或低电容存储单元的存储器件的本地数字线结构和方法
公开(公告)号：US07310257B2
公开(公告)日：2007-12-18
申请号：US11271024
申请日：2005-11-10
申请人： H. Montgomery Manning , Howard Kirsch
发明人： H. Montgomery Manning , Howard Kirsch
IPC分类号： G11C5/06 , G11C8/00
CPC分类号： G11C11/565 , G11C7/12 , G11C7/18 , G11C11/4094 , G11C11/4097
摘要： A DRAM array includes for each column a pair of complimentary digit lines that are coupled to a sense amplifier. Each of the global digit lines is selectively coupled to a plurality of local digit lines by respective coupling circuits. The length of the local digit lines is substantially shorter than the length of the global digit lines. As a result, the local digit lines have substantially less capacitance so that a voltage stored by a memory cell capacitor can be more easily transferred to the local digit line. The coupling circuits provide current amplification so that the voltage on the local digit lines can be more easily transferred to the global digit lines. A write back circuit is coupled to the local digit line to restore the voltage of the memory cell capacitor.
摘要翻译： DRAM阵列包括用于每列的耦合到读出放大器的一对互补数字线。每个全局数字线通过相应的耦合电路选择性地耦合到多个本地数字线。局部数字线的长度明显短于全局数字线的长度。结果，本地数字线具有实质上更小的电容，使得由存储单元电容器存储的电压可以更容易地传送到本地数字线。耦合电路提供电流放大，使得局部数字线上的电压可以更容易地传输到全局数字线。写回电路耦合到本地数字线以恢复存储单元电容器的电压。

2. 发明申请

US20060268640A1 Open digit line array architecture for a memory array 有权
公开(公告)号：US20060268640A1
公开(公告)日：2006-11-30
申请号：US11501144
申请日：2006-08-07
申请人： Sei Yoon , Charles Ingalls , David Pinney , Howard Kirsch
发明人： Sei Yoon , Charles Ingalls , David Pinney , Howard Kirsch
IPC分类号： G11C7/00
CPC分类号： G11C7/18 , G11C7/04 , G11C7/065 , G11C7/12 , G11C7/14 , G11C11/4091 , G11C11/4094 , G11C11/4097
摘要： A system and method for sensing a data state stored by a memory cell that includes coupling a first digit line and a second digit line to a precharge voltage and further coupling a memory cell to the first digit line. At least one digit line other than the first and second digit lines is driven to a reference voltage level and the at least one digit line is coupled to the second digit line to establish a reference voltage in the second digit line. A voltage differential is sensed between the first digit line and the second digit line, and a data state based on the voltage differential is latched in response.

3. 发明申请

US20050275430A1 Voltage level shifting circuit and method 失效
标题翻译：电压电平移位电路及方法
公开(公告)号：US20050275430A1
公开(公告)日：2005-12-15
申请号：US10868468
申请日：2004-06-14
申请人： Tae Kim , Howard Kirsch
发明人： Tae Kim , Howard Kirsch
IPC分类号： H03K3/356 , H03K19/0175
CPC分类号： H03K3/356113 , H03K3/356165
摘要： A voltage level shifting circuit and method that can be used for shifting the voltage level of an input signal to provide an output signal having a higher output voltage level. The voltage level shifting circuit includes pull-up transistors that are switched OFF by the voltage of a pair of switching nodes and not the voltage at the output node. The speed at which the pull-up transistors can be switched OFF is decoupled to some extent from the speed at which the voltage at the output node changes. Additionally, having the output node separated from the nodes that switch the pull-up transistors OFF further allows for dimensions of the various transistors of the voltage level shifting circuit to be scaled advantageously.
摘要翻译：一种电压电平移动电路和方法，可用于移位输入信号的电压电平以提供具有较高输出电压电平的输出信号。电压电平移位电路包括被一对开关节点的电压切断的上拉晶体管，而不是输出节点处的电压。上拉晶体管可以关断的速度在一定程度上与输出节点处的电压变化的速度解耦。另外，将输出节点与将上拉晶体管断开的节点分开的输出节点进一步允许电压电平移位电路的各种晶体管的尺寸被有利地缩放。

4. 发明申请

US20070268764A1 Low voltage sense amplifier and sensing method 有权
标题翻译：低电压检测放大器和感测方式
公开(公告)号：US20070268764A1
公开(公告)日：2007-11-22
申请号：US11436863
申请日：2006-05-17
申请人： Tae Kim , Charles L. Ingalls , David Pinney , Howard Kirsch
发明人： Tae Kim , Charles L. Ingalls , David Pinney , Howard Kirsch
IPC分类号： G11C7/00
CPC分类号： G11C7/08 , G11C7/065 , G11C7/12 , G11C11/4091 , G11C11/4094 , G11C2207/005 , G11C2207/2227
摘要： Systems and methods of sensing a data state coupled to a digit line and for coupling a digit line to a sense amplifier. In sensing the data state coupled to the digit line, the digit line is coupled to a sense node and driving voltages provided to the sense amplifier. The data state is latched in response to the driving voltages. In coupling the digit line to a sense amplifier, the digit line is coupled to the sense amplifier for a first time period and decoupled from the sense amplifier for a second time period. The digit line is coupled to the sense amplifier at a controlled rate following the second time period.
摘要翻译：感测耦合到数字线并且将数字线耦合到读出放大器的数据状态的系统和方法。在感测耦合到数字线的数据状态时，数字线耦合到感测节点并且提供给读出放大器的驱动电压。响应于驱动电压而锁存数据状态。在将数字线耦合到读出放大器时，数字线在第一时间段耦合到读出放大器，并在第二时间段内从读出放大器去耦。数字线以跟随第二时间段的受控速率耦合到读出放大器。

5. 发明申请

US20060044921A1 Memory devices having reduced coupling noise between wordlines 有权
公开(公告)号：US20060044921A1
公开(公告)日：2006-03-02
申请号：US10928034
申请日：2004-08-27
申请人： Tae Kim , Charles Ingalls , Howard Kirsch , Jeremy Gum
发明人： Tae Kim , Charles Ingalls , Howard Kirsch , Jeremy Gum
IPC分类号： G11C8/00
CPC分类号： G11C8/08
摘要： Memory devices configured to reduce coupling noise between adjacent wordlines in a memory array. More specifically, wordline drivers are interleaved such that adjacent wordlines are driven by wordline drivers enabled by different row decoders. Each wordline driver includes a weak transistor to ground and a strong transistor to ground. By disabling the wordline driver on the wordlines directly adjacent to the active wordlines, a path is provided to drive the coupling noise from the active wordline to ground through the strong transistor.

6. 发明申请

US20060044888A1 Level shifter for low voltage operation 有权
标题翻译：电平移位器用于低电压工作
公开(公告)号：US20060044888A1
公开(公告)日：2006-03-02
申请号：US10931587
申请日：2004-09-01
申请人： Tae Kim , Michael Cordoba , Howard Kirsch
发明人： Tae Kim , Michael Cordoba , Howard Kirsch
IPC分类号： G11C7/00
CPC分类号： G11C5/147 , G11C16/30 , H03K3/356113
摘要： A voltage level translator boosts the gate voltage of a transistor, and increases the gate to source voltage, to allow operation over a wider range of supply voltages. The P/N ratio of transistors in the voltage level translator is therefore increased, and control of the flipping of nodes is dependent on gate voltages as opposed to P/N ratios.
摘要翻译：电压电平转换器提高晶体管的栅极电压，并增加栅极到源极电压，以允许在更宽的电源电压范围内工作。因此，电压电平转换器中的晶体管的P / N比被增加，并且节点的翻转的控制取决于栅极电压而不是P / N比。

7. 发明申请

US20060043455A1 Multiple-depth STI trenches in integrated circuit fabrication 有权
标题翻译：集成电路制造中的多深STI沟槽
公开(公告)号：US20060043455A1
公开(公告)日：2006-03-02
申请号：US10931946
申请日：2004-09-01
申请人： Shubneesh Batra , Howard Kirsch , Gurtej Sandhu , Xianfeng Zhou , Chih-Chen Cho
发明人： Shubneesh Batra , Howard Kirsch , Gurtej Sandhu , Xianfeng Zhou , Chih-Chen Cho
IPC分类号： H01L21/76 , H01L29/76
CPC分类号： H01L21/76229
摘要： Multiple trench depths within an integrated circuit device are formed by first forming trenches in a substrate to a first depth, but of varying widths. Formation of a dielectric layer can cause some of the trenches to fill or close off while leaving other, wider trenches open. Removal of a portion of the dielectric material can then be tailored to expose a bottom of the open trenches while leaving remaining trenches filled. Removal of exposed portions of the underlying substrate can then be used to selectively deepen the open trenches, which can subsequently be filled. Such methods can be used to form trenches of varying depths without the need for subsequent masking.
摘要翻译：集成电路器件内的多个沟槽深度通过首先将衬底中的沟槽形成第一深度但具有变化的宽度来形成。电介质层的形成可以使一些沟槽填充或封闭，同时留下其他更宽的沟槽打开。然后可以去除电介质材料的一部分以暴露开口沟槽的底部，同时留下剩余的沟槽填充。然后可以去除下面的衬底的暴露部分以选择性地加深可以随后填充的开放沟槽。这种方法可用于形成不同深度的沟槽，而不需要随后的掩蔽。

8. 发明申请

US20090168551A1 LOW VOLTAGE SENSE AMPLIFIER AND SENSING METHOD 有权
标题翻译：低电压检测放大器和感测方法
公开(公告)号：US20090168551A1
公开(公告)日：2009-07-02
申请号：US12399757
申请日：2009-03-06
申请人： Tae Kim , Charles L. Ingalls , David Pinney , Howard Kirsch
发明人： Tae Kim , Charles L. Ingalls , David Pinney , Howard Kirsch
IPC分类号： G11C7/00 , G11C7/06 , G11C5/14
CPC分类号： G11C7/08 , G11C7/065 , G11C7/12 , G11C11/4091 , G11C11/4094 , G11C2207/005 , G11C2207/2227
摘要： Systems and methods of sensing a data state coupled to a digit line and for coupling a digit line to a sense amplifier. In sensing the data state coupled to the digit line, the digit line is coupled to a sense node and driving voltages provided to the sense amplifier. The data state is latched in response to the driving voltages. In coupling the digit line to a sense amplifier, the digit line is coupled to the sense amplifier for a first time period and decoupled from the sense amplifier for a second time period. The digit line is coupled to the sense amplifier at a controlled rate following the second time period.
摘要翻译：感测耦合到数字线并且将数字线耦合到读出放大器的数据状态的系统和方法。在感测耦合到数字线的数据状态时，数字线耦合到感测节点并且提供给读出放大器的驱动电压。响应于驱动电压而锁存数据状态。在将数字线耦合到读出放大器时，数字线在第一时间段耦合到读出放大器，并在第二时间段内从读出放大器去耦。数字线以跟随第二时间段的受控速率耦合到读出放大器。

9. 发明授权

US07535282B2 Dynamic well bias controlled by Vt detector 有权
标题翻译： Vt检测器控制动态阱偏置
公开(公告)号：US07535282B2
公开(公告)日：2009-05-19
申请号：US11146852
申请日：2005-06-07
申请人： Tae Kim , Howard Kirsch , Charles Ingalls , David Pinney
发明人： Tae Kim , Howard Kirsch , Charles Ingalls , David Pinney
IPC分类号： H03K19/017 , G05F1/575 , H01L27/04
CPC分类号： G05F3/205 , H03K17/302
摘要： The p- well back bias for NCH transistors in a DRAM sense amplifier circuit is dynamically adjusted. Preferably, during sensing, the p- well back bias for the NCH transistors of the sense amp is increased to in effect lower the threshold voltages for the NCH transistors so that they are more easily activated during sensing. The back bias voltage is preferably increased from ground (its normal value) to the threshold voltage of a NCH transistor (NVt), a value low enough to prevent the circuit from latch-up. Moreover, this voltage is preferably arrived at using a Vt detector/bias circuitry which receives the p- well bias voltage as feedback. While benefiting the disclosed sense amp circuit, the dynamic bias provided to the p- well of the NCH transistors can also benefit NCH transistors in other CMOS circuitry as well. Moreover, similar modifications to dynamically bias the n- wells of PCH transistors in CMOS circuits are also provided to increase the sensing margins of PCH transistors as well.
摘要翻译：动态地调整DRAM读出放大器电路中的NCH晶体管的p阱背偏置。优选地，在感测期间，感测放大器的NCH晶体管的p阱反向偏置被增加以实际上降低NCH晶体管的阈值电压，使得它们在感测期间更容易被激活。背偏置电压优选地从地（其正常值）增加到NCH晶体管（NVt）的阈值电压，其值足够低以防止电路闭锁。此外，该电压优选地使用接收p阱偏置电压作为反馈的Vt检测器/偏置电路来实现。在使公开的感测放大器电路受益的同时，提供给NCH晶体管的p阱的动态偏置也可以有益于其它CMOS电路中的NCH晶体管。此外，还提供了对CMOS电路中的PCH晶体管的n阱动态偏置的类似修改，以增加PCH晶体管的感测裕度。

10. 发明申请

US20090108292A1 Floating Body Field-Effect Transistors, and Methods of Forming Floating Body Field-Effect Transistors 有权
标题翻译：浮体场效应晶体管，以及形成浮体场效应晶体管的方法
公开(公告)号：US20090108292A1
公开(公告)日：2009-04-30
申请号：US11925573
申请日：2007-10-26
申请人： Jun Liu , Michael P. Violette , Chandra Mouli , Howard Kirsch , Di Li
发明人： Jun Liu , Michael P. Violette , Chandra Mouli , Howard Kirsch , Di Li
IPC分类号： H01L29/778 , H01L21/336 , H01L29/786
CPC分类号： H01L27/1203 , H01L27/10802 , H01L29/66477 , H01L29/7841 , H01L2924/0002 , H01L2924/00
摘要： In one embodiment, a floating body field-effect transistor includes a pair of source/drain regions having a floating body channel region received therebetween. The source/drain regions and the floating body channel region are received over an insulator. A gate electrode is proximate the floating body channel region. A gate dielectric is received between the gate electrode and the floating body channel region. The floating body channel region has a semiconductor SixGe(1-x)-comprising region. The floating body channel region has a semiconductor silicon-comprising region received between the semiconductor SixGe(1-x)-comprising region and the gate dielectric. The semiconductor SixGe(1-x)-comprising region has greater quantity of Ge than any quantity of Ge within the semiconductor silicon-comprising region. Other embodiments are contemplated, including methods of forming floating body field-effect transistors.
摘要翻译：在一个实施例中，浮体场效应晶体管包括一对在其间容纳浮体通道区的源/漏区。源极/漏极区域和浮体沟道区域被接纳在绝缘体上。栅电极靠近浮体通道区域。门电介质被接收在栅电极和浮体沟道区之间。浮体通道区域具有半导体SixGe（1-x）区域。浮体通道区域具有容纳在半导体SixGe（1-x）区域和栅极电介质之间的半导体硅包覆区域。半导体SixGe（1-x）含量区域在含半导体硅的区域内具有比任何Ge量更大的Ge量。考虑了其他实施例，包括形成浮体场效应晶体管的方法。

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