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1. 发明授权

US08489781B1 Detection system and methods 有权
标题翻译：检测系统和方法
公开(公告)号：US08489781B1
公开(公告)日：2013-07-16
申请号：US12721268
申请日：2010-03-10
申请人： Hongming An , CongQing Xiong , Heng Wang
发明人： Hongming An , CongQing Xiong , Heng Wang
IPC分类号： G06F3/00 , H02J7/00
CPC分类号： G06F13/4295 , H02J7/0036 , H02J2007/0062
摘要： Various techniques are provided to facilitate a detection system to detect a presence of an externally coupled receiver device, such as a universal serial bus (USB) device. In one example, the system generates a reference current and passes the reference current via a conductor to a shared buffer circuit. The shared buffer circuit is adapted to selectively pass the reference current or a communication signal to the externally coupled receiver device. The system switches between a detect mode where the reference current is provided to the externally coupled receiver device and between a communicate mode where the reference current is blocked and the communication signal is provided to the externally coupled receiver device. The system monitors a voltage value of the conductor and the system monitors a time for the voltage value to reach a pre-determined threshold value in response to the reference current. The system detects a presence of the externally coupled receiver device based on the monitored time.
摘要翻译：提供各种技术以便于检测系统检测诸如通用串行总线（USB）设备之类的外部耦合的接收机设备的存在。在一个示例中，系统产生参考电流并且经由导体将参考电流传递到共享缓冲器电路。共享缓冲电路适于选择性地将参考电流或通信信号传递到外部耦合的接收机设备。系统在提供参考电流的检测模式与外部耦合的接收机设备之间以及在参考电流被阻挡的通信模式与通信信号提供给外部耦合的接收机设备之间切换。该系统监视导体的电压值，并且系统监视响应于参考电流的电压值达到预定阈值的时间。该系统基于所监视的时间来检测外部耦合的接收机设备的存在。

2. 发明授权

US07826563B2 High speed multi-modulus prescalar divider 有权
标题翻译：高速多模式预分频器
公开(公告)号：US07826563B2
公开(公告)日：2010-11-02
申请号：US11717262
申请日：2007-03-13
申请人： Hongming An , Simon Pang , Viet Linh Do
发明人： Hongming An , Simon Pang , Viet Linh Do
IPC分类号： H03D3/24
CPC分类号： H03L7/193 , G06F7/68 , H03K23/68
摘要： A system and method are provided for multi-modulus division. The method accepts an input first signal having a first frequency and divides the first frequency by an integral number. A second signal is generated with a plurality of phase outputs, each having a second frequency. Using a daisy-chain register controller, phase outputs are selected and supplied as a third signal with a frequency. Selecting phase outputs using the daisy-chain register controller includes supplying the third signal as a clock signal to registers having outputs connected in a daisy-chain. Then, a sequence of register output pulses is generated in response to the clock signals, and register output pulses are chosen from the sequence to select second signal phase outputs. By using 8-second signal phase outputs, a third signal is obtained with a frequency equal to the second frequency multiplied by one of the following numbers: 0.75, 0.875, 1, 1.125, or 1.25.
摘要翻译：提供了一种用于多模式分割的系统和方法。该方法接受具有第一频率的输入第一信号，并将第一频率除以整数。利用具有第二频率的多个相位输出产生第二信号。使用菊花链寄存器控制器，相位输出被选择并作为具有频率的第三个信号提供。使用菊花链寄存器控制器选择相位输出包括将第三个信号作为时钟信号提供给具有以菊花链连接的输出的寄存器。然后，响应于时钟信号产生寄存器输出脉冲序列，并且从序列中选择寄存器输出脉冲以选择第二信号相位输出。通过使用8秒信号相位输出，获得第三个信号，频率等于第二个频率乘以以下数字之一：0.75,0.875,1,1125或1.25。

3. 发明申请

US20100052817A1 Integrated Circuit Inductor with Transverse Interfaces 有权
标题翻译：具有横向接口的集成电路电感器
公开(公告)号：US20100052817A1
公开(公告)日：2010-03-04
申请号：US12408606
申请日：2009-03-20
申请人： Siqi Fan , Hongming An
发明人： Siqi Fan , Hongming An
IPC分类号： H03H7/01 , H01F5/00
CPC分类号： H01F17/0013 , H01F27/29 , H01F27/34 , H01F2017/0026 , H01F2017/0046 , H01F2017/0073 , H03H7/0115
摘要： An integrated circuit (IC) inductor structure is provided with transverse electrical interfaces. The inductor structure is formed on at least one IC circuit layer and has a first axis planar to a circuit layer surface, bisecting the inductor into opposite first and second sides. An input interface is formed on the circuit layer and connected to the inductor first side, parallel to a second axis, which is perpendicular to the first axis. An output interface is formed on the circuit layer and connected to the inductor second side, parallel to the second axis. In one aspect, the inductor has a center tap electrical interface parallel to the axis. In another aspect, the inductor includes a three-dimensional (3D) loop formed over a plurality of the circuit layers.
摘要翻译：集成电路（IC）电感器结构具有横向电接口。电感器结构形成在至少一个IC电路层上，并且具有与电路层表面平面的第一轴，将电感器平分成相对的第一和第二侧。输入接口形成在电路层上，并且连接到电感器第一侧，平行于垂直于第一轴的第二轴线。输出接口形成在电路层上，并连接到电感器第二侧，平行于第二轴。在一个方面，电感器具有平行于该轴线的中心抽头电接口。在另一方面，电感器包括形成在多个电路层上的三维（3D）环路。

4. 发明申请

US20080225989A1 High speed multi-modulus prescalar divider 有权
标题翻译：高速多模式预分频器
公开(公告)号：US20080225989A1
公开(公告)日：2008-09-18
申请号：US11717262
申请日：2007-03-13
申请人： Hongming An , Simon Pang , Viet Linh Do
发明人： Hongming An , Simon Pang , Viet Linh Do
IPC分类号： H04L27/00
CPC分类号： H03L7/193 , G06F7/68 , H03K23/68
摘要： A system and method are provided for multi-modulus division. The method accepts an input first signal having a first frequency and divides the first frequency by an integral number. A second signal is generated with a plurality of phase outputs, each having a second frequency. Using a daisy-chain register controller, phase outputs are selected and supplied as a third signal with a frequency. Selecting phase outputs using the daisy-chain register controller includes supplying the third signal as a clock signal to registers having outputs connected in a daisy-chain. Then, a sequence of register output pulses is generated in response to the clock signals, and register output pulses are chosen from the sequence to select second signal phase outputs. By using 8-second signal phase outputs, a third signal is obtained with a frequency equal to the second frequency multiplied by one of the following numbers: 0.75, 0.875, 1, 1.125, or 1.25.
摘要翻译：提供了一种用于多模式分割的系统和方法。该方法接受具有第一频率的输入第一信号，并将第一频率除以整数。利用具有第二频率的多个相位输出产生第二信号。使用菊花链寄存器控制器，相位输出被选择并作为具有频率的第三个信号提供。使用菊花链寄存器控制器选择相位输出包括将第三个信号作为时钟信号提供给具有以菊花链连接的输出的寄存器。然后，响应于时钟信号产生寄存器输出脉冲序列，并且从序列中选择寄存器输出脉冲以选择第二信号相位输出。通过使用8秒信号相位输出，获得第三个信号，频率等于第二个频率乘以以下数字之一：0.75,0.875,1,1125或1.25。

5. 发明申请

US20080224735A1 Frequency Synthesis Rational Division 有权
标题翻译：频率综合理科
公开(公告)号：US20080224735A1
公开(公告)日：2008-09-18
申请号：US12120027
申请日：2008-05-13
申请人： Viet Linh Do , Simon Pang , Hongming An , Jim Lew
发明人： Viet Linh Do , Simon Pang , Hongming An , Jim Lew
IPC分类号： H03B21/00
CPC分类号： H03L7/1976 , G06F7/68 , H03K23/486
摘要： A system and method are provided for synthesizing signal frequencies using rational division. The method accepts a reference frequency value and a synthesized frequency value. In response to dividing the synthesized frequency value by the reference frequency value, an integer value numerator (dp) and an integer value denominator (dq) are determined. The method reduces the ratio of dp/dq to an integer N and a ratio of p/q (dp/dq=N(p/q)), where p/q
摘要翻译：提供了一种使用合理划分来合成信号频率的系统和方法。该方法接受参考频率值和合成频率值。响应于将合成频率值除以参考频率值，确定整数值分子（dp）和整数值分母（dq）。该方法降低了dp / dq与整数N的比值和p / q（dp / dq = N（p / q））的比值，其中p / q <1（十进制）。分子（p）和分母（q）被提供给灵活的累加器模块，因此产生除数。 N与k位商相加以创建除数。在锁相环（PLL）中，除数和参考信号用于产生频率等于合成频率值的合成信号。

6. 发明授权

US08443023B2 Frequency synthesis rational division 有权
标题翻译：频率综合理性分割
公开(公告)号：US08443023B2
公开(公告)日：2013-05-14
申请号：US12120027
申请日：2008-05-13
申请人： Viet Linh Do , Simon Pang , Hongming An , Jim Lew
发明人： Viet Linh Do , Simon Pang , Hongming An , Jim Lew
IPC分类号： G06F1/02
CPC分类号： H03L7/1976 , G06F7/68 , H03K23/486
摘要： A system and method are provided for synthesizing signal frequencies using rational division. The method accepts a reference frequency value and a synthesized frequency value. In response to dividing the synthesized frequency value by the reference frequency value, an integer value numerator (dp) and an integer value denominator (dq) are determined. The method reduces the ratio of dp/dq to an integer N and a ratio of p/q (dp/dq=N(p/q)), where p/q
摘要翻译：提供了一种使用合理划分来合成信号频率的系统和方法。该方法接受参考频率值和合成频率值。响应于将合成频率值除以参考频率值，确定整数值分子（dp）和整数值分母（dq）。该方法降低了dp / dq与整数N的比值和p / q（dp / dq = N（p / q））的比率，其中p / q <1（十进制）。分子（p）和分母（q）被提供给灵活的累加器模块，因此产生除数。 N与k位商相加以创建除数。在锁相环（PLL）中，除数和参考信号用于产生频率等于合成频率值的合成信号。

7. 发明授权

US08013689B2 Integrated circuit inductor with transverse interfaces 有权
标题翻译：集成电路电感与横向接口
公开(公告)号：US08013689B2
公开(公告)日：2011-09-06
申请号：US12408606
申请日：2009-03-20
申请人： Siqi Fan , Hongming An
发明人： Siqi Fan , Hongming An
IPC分类号： H03H7/01
CPC分类号： H01F17/0013 , H01F27/29 , H01F27/34 , H01F2017/0026 , H01F2017/0046 , H01F2017/0073 , H03H7/0115
摘要： An integrated circuit (IC) inductor structure is provided with transverse electrical interfaces. The inductor structure is formed on at least one IC circuit layer and has a first axis planar to a circuit layer surface, bisecting the inductor into opposite first and second sides. An input interface is formed on the circuit layer and connected to the inductor first side, parallel to a second axis, which is perpendicular to the first axis. An output interface is formed on the circuit layer and connected to the inductor second side, parallel to the second axis. In one aspect, the inductor has a center tap electrical interface parallel to the axis. In another aspect, the inductor includes a three-dimensional (3D) loop formed over a plurality of the circuit layers.
摘要翻译：集成电路（IC）电感器结构具有横向电接口。电感器结构形成在至少一个IC电路层上，并且具有与电路层表面平面的第一轴，将电感器平分成相对的第一和第二侧。输入接口形成在电路层上，并且连接到电感器第一侧，平行于垂直于第一轴的第二轴线。输出接口形成在电路层上，并连接到电感器第二侧，平行于第二轴。在一个方面，电感器具有平行于该轴线的中心抽头电接口。在另一方面，电感器包括形成在多个电路层上的三维（3D）环路。

8. 发明授权

US07990296B1 High speed low power cell providing serial differential signals 有权
标题翻译：高速低功率电池提供串行差分信号
公开(公告)号：US07990296B1
公开(公告)日：2011-08-02
申请号：US12721418
申请日：2010-03-10
申请人： Heng Wang , Hongming An , CongQing Xiong
发明人： Heng Wang , Hongming An , CongQing Xiong
IPC分类号： H03M9/00
CPC分类号： H03M9/00
摘要： Techniques are provided to serialize and delay parallel input data signals and are particularly useful for low power applications. In one example, a device includes a plurality of data input ports adapted to receive N parallel single-ended input data signals, and a clock input port adapted to receive a clock signal substantially synchronized with the parallel single-ended input data signals. The device also includes a cell adapted to serialize the parallel single-ended input data signals to provide N/2 first serial differential output data signals in response to the clock signal, delay the parallel single-ended input data signals, and serialize the delayed parallel single-ended input data signals to provide N/2 delayed second serial differential output data signals in response to the clock signal. The delayed second serial differential output data signals are delayed relative to the first serial differential output data signals. The device also includes a plurality of output ports.
摘要翻译：提供技术来串行化和延迟并行输入数据信号，并且对于低功率应用特别有用。在一个示例中，设备包括适于接收N个并行单端输入数据信号的多个数据输入端口和适于接收与并行单端输入数据信号基本同步的时钟信号的时钟输入端口。该器件还包括适用于串行化并行单端输入数据信号的单元，以响应于时钟信号提供N / 2个第一串行差分输出数据信号，延迟并行单端输入数据信号，并串行化延迟并联单端输入数据信号，以响应于时钟信号提供N / 2延迟的第二串行差分输出数据信号。延迟的第二串行差分输出数据信号相对于第一串行差分输出数据信号被延迟。该设备还包括多个输出端口。

9. 发明授权

US07525382B2 Multi-level slew and swing control buffer 有权
标题翻译：多级摆动和摆动控制缓冲器
公开(公告)号：US07525382B2
公开(公告)日：2009-04-28
申请号：US11888921
申请日：2007-08-04
申请人： Hongming An , Sudhaker Anumula , Howard Chang
发明人： Hongming An , Sudhaker Anumula , Howard Chang
IPC分类号： H03F3/45
CPC分类号： H03F3/45475 , H03F3/45183 , H03F2200/405 , H03F2203/45248 , H03F2203/45454 , H03F2203/45466 , H03F2203/45471 , H03F2203/45702
摘要： A buffer amplifier and an associated method have been provided for slew rate and swing level control in the buffering of a signal. The method accepts an input signal having a voltage swing, a swing control signal, and a slew rate control signal. The voltage swing for each output in a set of serially-connected buffer stages is selected in response to the swing control signal. The selected voltage swing for a subset of buffer stages is modified in response to the slew rate control signal. Selecting the voltage swing for each output entails selecting a source current for each buffer stage. A bias current is generated and mirrored through a current source connected to each buffer stage. Modifying the selected voltage swing for each of the subset of buffer stages includes modifying the bias current to the subset of buffer stages.
摘要翻译：已经提供了用于缓冲信号的压摆率和摆幅电平控制的缓冲放大器和相关联的方法。该方法接受具有电压摆幅，摆动控制信号和转换速率控制信号的输入信号。响应于摆动控制信号选择一组串联缓冲级中的每个输出的电压摆幅。响应于压摆率控制信号修改缓冲级子集的所选电压摆幅。为每个输出选择电压摆幅需要为每个缓冲段选择一个源电流。通过连接到每个缓冲级的电流源产生和镜像偏置电流。对缓冲器级的每个子集修改所选择的电压摆幅包括将偏置电流修改到缓冲器级的子集。

10. 发明申请

US20090033422A1 Multi-level slew and swing control buffer 有权
公开(公告)号：US20090033422A1
公开(公告)日：2009-02-05
申请号：US11888921
申请日：2007-08-04
申请人： Hongming An , Sudhaker Anumula , Howard Chang
发明人： Hongming An , Sudhaker Anumula , Howard Chang
IPC分类号： H03F3/45
CPC分类号： H03F3/45475 , H03F3/45183 , H03F2200/405 , H03F2203/45248 , H03F2203/45454 , H03F2203/45466 , H03F2203/45471 , H03F2203/45702
摘要： A buffer amplifier and an associated method have been provided for slew rate and swing level control in the buffering of a signal. The method accepts an input signal having a voltage swing, a swing control signal, and a slew rate control signal. The voltage swing for each output in a set of serially-connected buffer stages is selected in response to the swing control signal. The selected voltage swing for a subset of buffer stages is modified in response to the slew rate control signal. Selecting the voltage swing for each output entails selecting a source current for each buffer stage. A bias current is generated and mirrored through a current source connected to each buffer stage. Modifying the selected voltage swing for each of the subset of buffer stages includes modifying the bias current to the subset of buffer stages.

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