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    • 9. 发明授权
    • ESD protection for high voltage level input for analog application
    • 用于模拟应用的高电压电平输入的ESD保护
    • US6002567A
    • 1999-12-14
    • US953184
    • 1997-10-17
    • ZhiYuan ZouHoang P. Nguyen
    • ZhiYuan ZouHoang P. Nguyen
    • H01L27/02H02H3/22
    • H01L27/0248
    • The present invention provides for ESD protection while allowing the use of an input signal that is higher than V.sub.DD. The present invention preferably includes a protection device and a delay circuit coupled to an input pad and to a ground reference. The protection device is a preferred silicon controlled rectifier, and the delay circuit is preferably a low pass filter RC circuit that includes a resistor and a capacitor. A node associated with the delay circuit is coupled to circuitry of an integrated circuit. The circuitry has associated therewith at least one gate oxide breakdown voltage. A gate oxide breakdown voltage is prevented from being applied to the circuitry of the integrated circuit. When an ESD voltage is applied to the input pad, the voltage at that pad ramps or increases quickly. The delay circuit prevents the node from ramping as quickly by delaying the ramping or increasing of the node voltage. This delay provides time for the protection device to turn on and sink the ESD current.
    • 本发明提供ESD保护,同时允许使用高于VDD的输入信号。 本发明优选地包括保护装置和耦合到输入焊盘和接地参考的延迟电路。 保护装置是优选的可控硅整流器,并且延迟电路优选地是包括电阻器和电容器的低通滤波器RC电路。 与延迟电路相关联的节点耦合到集成电路的电路。 该电路具有至少一个栅极氧化物击穿电压。 防止栅极氧化物击穿电压施加到集成电路的电路。 当ESD电压施加到输入焊盘时,该焊盘处的电压斜坡上升或迅速增加。 延迟电路通过延迟节点电压的斜坡或增加来防止节点快速斜坡。 该延迟为保护装置打开和吸收ESD电流提供了时间。
    • 10. 发明授权
    • Meta-hardened flip-flop
    • 元硬化触发器
    • US5999029A
    • 1999-12-07
    • US671862
    • 1996-06-28
    • Hoang P. NguyenRichard T. Schultz
    • Hoang P. NguyenRichard T. Schultz
    • H03K3/037
    • H03K3/0375
    • A meta-hardened circuit that reduces the effects of metastability preferably includes a pulse generator coupled to receive a first clock signal and generate in response thereto a second clock signal and an enable signal. A buffer, preferably tri-state, is coupled to receive a first data signal and the enable signal and generate in response thereto a second data signal. A bi-stable device, such as a flip-flop, is coupled to receive the second clock signal and the second data signal. The pulse generator preferably includes a combining device and a delay device. The buffer preferably includes at least one tri-state inverter and a keeper circuit. A method to reduce the metastability effects preferably includes the step of generating a delay between a second data input signal and a second clock signal that is greater than a delay between a first data input signal and a first clock signal. The step of generating preferably occurs in one clock cycle. The method also preferably includes generating an enable pulse by generating a second clock signal in response to a first clock signal and combining the first and second clock signals to generate the enable signal, and generating a second data input signal in response to a first data input signal, where generating the second data input signal includes receiving an enable signal. The method preferably includes the step of generating an output signal in response to the second data input signal and the second clock signal, the output signal having a reduced metastable effect.
    • 降低亚稳态影响的元硬化电路优选地包括脉冲发生器,其被耦合以接收第一时钟信号并响应于此产生第二时钟信号和使能信号。 耦合优选三态的缓冲器以接收第一数据信号和使能信号,并响应于此产生第二数据信号。 诸如触发器的双稳态器件被耦合以接收第二时钟信号和第二数据信号。 脉冲发生器优选地包括组合装置和延迟装置。 缓冲器优选地包括至少一个三态反相器和保持器电路。 降低亚稳效应的方法优选地包括产生第二数据输入信号和大于第一数据输入信号和第一时钟信号之间的延迟的第二时钟信号之间的延迟的步骤。 优选的发生步骤在一个时钟周期内发生。 该方法还优选地包括通过响应于第一时钟信号产生第二时钟信号并组合第一和第二时钟信号以产生使能信号来产生使能脉冲,以及响应于第一数据输入产生第二数据输入信号 信号,其中产生所述第二数据输入信号包括接收使能信号。 该方法优选地包括响应于第二数据输入信号和第二时钟信号产生输出信号的步骤,输出信号具有降低的亚稳效应。