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1. 发明授权

US08608378B2 Temperature measuring apparatus 有权
标题翻译：温度测量仪
公开(公告)号：US08608378B2
公开(公告)日：2013-12-17
申请号：US13516916
申请日：2010-12-06
申请人： Hisaki Ishida , Masato Hayashi , Koudai Higashi
发明人： Hisaki Ishida , Masato Hayashi , Koudai Higashi
IPC分类号： G01K7/00
CPC分类号： G01K1/18 , H01L21/67248 , H01L2224/48091 , H01L2224/8592 , H01L2924/00014
摘要： Disclosed is a temperature measuring apparatus which is provided with: a substrate (2); a temperature sensor (3) disposed on one surface of the substrate (2); and a wire (8) disposed to electrically connect together a circuit, which detects a temperature using the temperature sensor (3), and the temperature sensor (3). In said surface of the substrate (2), a recessed section (7) having a heat capacity smaller than that of the material of the substrate (2) is formed on the periphery of the temperature sensor (3). The recessed section (7) is formed at a predetermined interval from the temperature sensor (3) such that the recessed section surrounds the temperature sensor (3) and has predetermined width and depth. Preferably, the low heat capacity zone is the recessed section (7), i.e., the groove having a recessed cross-section.
摘要翻译：公开了一种温度测量装置，其设置有：基板（2）; 设置在所述基板（2）的一个表面上的温度传感器（3）; 以及布置成将使用温度传感器（3）检测温度的电路和温度传感器（3）电连接在一起的线（8）。在基板（2）的所述表面中，在温度传感器（3）的周围形成有具有小于基板（2）的材料的热容的凹部（7）。凹部（7）从温度传感器（3）以预定的间隔形成，使得凹部包围温度传感器（3）并且具有预定的宽度和深度。优选地，低热容区是凹部（7），即凹槽具有凹入的横截面。

2. 发明申请

US20110233546A1 WAFER-TYPE TEMPERATURE SENSOR AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译： WAFER型温度传感器及其制造方法
公开(公告)号：US20110233546A1
公开(公告)日：2011-09-29
申请号：US13053473
申请日：2011-03-22
申请人： Koudai Higashi , Masato Hayashi , Hisaki Ishida
发明人： Koudai Higashi , Masato Hayashi , Hisaki Ishida
IPC分类号： H01L29/66 , H01L21/50
CPC分类号： G01K13/10 , G01K13/00 , H01L21/67248
摘要： A wafer-type temperature sensor may include a wafer for temperature detection; a circuit board bonded to one surface of the wafer for temperature detection; at least one temperature data detector provided on the one surface of the wafer for temperature detection and capable of detecting temperature data; and a temperature detecting unit mounted on the circuit board and capable of detecting a temperature of the wafer for temperature detection from the temperature data detected by the temperature data detector. Here, a difference between a linear expansion coefficient of the circuit board and a linear expansion coefficient of the wafer for temperature detection may be equal to or less than a predetermined value.
摘要翻译：晶片型温度传感器可以包括用于温度检测的晶片; 结合到晶片的一个表面用于温度检测的电路板; 至少一个温度数据检测器，设置在晶片的一个表面上用于温度检测并且能够检测温度数据; 以及温度检测单元，其安装在电路板上，并能够根据由温度数据检测器检测到的温度数据检测用于温度检测的晶片的温度。这里，电路板的线膨胀系数与用于温度检测的晶片的线膨胀系数之间的差可以等于或小于预定值。

3. 发明授权

US06275420B1 Semiconductor device having memory cell part and transfer circuit 失效
标题翻译：具有存储单元部分和转移电路的半导体器件
公开(公告)号：US06275420B1
公开(公告)日：2001-08-14
申请号：US09552690
申请日：2000-04-19
申请人： Mikio Fujita , Hisaki Ishida
发明人： Mikio Fujita , Hisaki Ishida
IPC分类号： G11C700
CPC分类号： G11C7/1075 , G11C7/1006 , G11C2207/104
摘要： A semiconductor device includes a memory cell part which has data input terminals and which stores data received at the data input terminals and a data bus which is supplied with data. The semiconductor device also includes a transfer circuit which is coupled between the data bus and the data input terminals and which transfers the data from the data bus to the data input terminals in response to a transfer selection signal. The semiconductor device also includes a transfer control circuit which receives a bit selection signal and outputs the transfer selection signal.
摘要翻译：半导体器件包括具有数据输入端并存储在数据输入端子处接收的数据的存储单元部分和被提供有数据的数据总线。半导体器件还包括耦合在数据总线和数据输入端之间的传送电路，并且响应传输选择信号将数据从数据总线传送到数据输入端。半导体器件还包括接收位选择信号并输出传输选择信号的传输控制电路。

4. 发明授权

US5136292A Serial data receiving circuit for serial to parallel conversion 失效
标题翻译：串行数据接收电路，并行转换为并行转换
公开(公告)号：US5136292A
公开(公告)日：1992-08-04
申请号：US601799
申请日：1990-11-14
申请人： Hisaki Ishida
发明人： Hisaki Ishida
IPC分类号： G06F5/00 , H03M9/00
CPC分类号： H03M9/00 , G06F5/00 , G06F7/49994
摘要： A serial data receiving circuit comprising a most significant bit input detecting circuit (20) for providing a given control signal in synchronism with input of the most significant bit of a serial data represented by twos complement and a data converter circuit (30B) for subjecting the serial data to a sign extension data when the control signal is active and providing the resultant sign extended data as a parallel data and shifting the serial data from a low order bit to a high order bit when the control signal is inactive and providing the shifted data as a parallel data. The serial data receiving circuit further comprising a sign extension data processing circuit (40) for converting the serial data to the sign extension data on the basis of a format designating control signal so that the parallel data represented by sign extended twos complement is obtained upon reception of the serial input data in the twos complement representation having variable numbers of bits or the serial input data of the offset binary, straight binary, twos complement representation.
摘要翻译： PCT No.PCT / JP90 / 00331 Sec。 371日期1990年11月15日 102（e）1990年11月15日日期PCT 1990年3月14日提交PCT公布。 WO90 / 10903 PCT出版物日期1990年9月20日。一种串行数据接收电路，包括最高有效位输入检测电路（20），用于与由二进制补码和数据转换器表示的串行数据的最高有效位的输入同步地提供给定的控制信号电路（30B），用于当控制信号有效时对串行数据进行符号扩展数据，并将合成的符号扩展数据提供为并行数据，并且当串行数据从低位转换到高位时，控制信号是非活动的，并将移位的数据提供为并行数据。串行数据接收电路还包括符号扩展数据处理电路（40），用于根据格式指定控制信号将串行数据转换为符号扩展数据，使得在接收时获得由符号扩展二进制补码表示的并行数据具有可变位数的二进制补码表示中的串行输入数据或偏移二进制，直的二进制，二进制补码表示的串行输入数据。

5. 发明申请

US20120269229A1 TEMPERATURE MEASURING APPARATUS 有权
标题翻译：温度测量装置
公开(公告)号：US20120269229A1
公开(公告)日：2012-10-25
申请号：US13516916
申请日：2010-12-06
申请人： Hisaki Ishida , Masato Hayashi , Koudai Higashi
发明人： Hisaki Ishida , Masato Hayashi , Koudai Higashi
IPC分类号： G01K7/00 , G01K7/16
CPC分类号： G01K1/18 , H01L21/67248 , H01L2224/48091 , H01L2224/8592 , H01L2924/00014
摘要： Disclosed is a temperature measuring apparatus which is provided with: a substrate (2); a temperature sensor (3) disposed on one surface of the substrate (2); and a wire (8) disposed to electrically connect together a circuit, which detects a temperature using the temperature sensor (3), and the temperature sensor (3). In said surface of the substrate (2), a recessed section (7) having a heat capacity smaller than that of the material of the substrate (2) is formed on the periphery of the temperature sensor (3). The recessed section (7) is formed at a predetermined interval from the temperature sensor (3) such that the recessed section surrounds the temperature sensor (3) and has predetermined width and depth. Preferably, the low heat capacity zone is the recessed section (7), i.e., the groove having a recessed cross-section.
摘要翻译：公开了一种温度测量装置，其设置有：基板（2）; 设置在所述基板（2）的一个表面上的温度传感器（3）; 以及布置成将使用温度传感器（3）检测温度的电路和温度传感器（3）电连接在一起的线（8）。在基板（2）的所述表面中，在温度传感器（3）的周围形成有具有小于基板（2）的材料的热容的凹部（7）。凹部（7）从温度传感器（3）以预定的间隔形成，使得凹部包围温度传感器（3）并且具有预定的宽度和深度。优选地，低热容区是凹部（7），即凹槽具有凹入的横截面。

6. 发明授权

US4982355A Low-power parallel multiplier 失效
标题翻译：低功率并行乘法器
公开(公告)号：US4982355A
公开(公告)日：1991-01-01
申请号：US300492
申请日：1989-01-20
申请人： Eiichi Nishimura , Takao Nakamura , Hisaki Ishida
发明人： Eiichi Nishimura , Takao Nakamura , Hisaki Ishida
IPC分类号： G06F7/53 , G06F7/508 , G06F7/52 , G06F7/76
CPC分类号： G06F7/5312 , G06F7/762
摘要： A parallel multiplier consists of a systolic array of AND gates and full adders organized in stages so that each stage generates a partial product, adds it to the preceding partial products, and furnishes the sum to the next stage. A control circuit is provided that disables the outputs of each stage of the array until the operation in the particular stage is completed. The disabling of outputs reduces power consumption.
摘要翻译：并行乘法器由AND门的收缩阵列和分阶段组合的全加法器组成，使得每个阶段生成部分乘积，将其添加到先前的部分乘积，并将总和提供给下一个阶段。提供了一种控制电路，其禁用阵列的每个级的输出，直到特定级的操作完成。输出禁用可以降低功耗。

7. 发明授权

US5010510A Multiplying unit circuit 失效
标题翻译：乘法单元电路
公开(公告)号：US5010510A
公开(公告)日：1991-04-23
申请号：US579343
申请日：1990-09-07
申请人： Eiichi Nishimura , Takao Nakamura , Hisaki Ishida
发明人： Eiichi Nishimura , Takao Nakamura , Hisaki Ishida
IPC分类号： G06F7/53 , G06F7/508 , G06F7/52 , G06F7/76
CPC分类号： G06F7/5312 , G06F7/762
摘要： A parallel multiplier consists of a systolic array of AND gates and full adders organized in stages so that each stage generates a partial product, adds it to the preceding partial products, and furnishes the sum to the next stage. A control circuit is provided that disables the outputs of each stage of the array until the operation in the particular stage is completed. The disabling of outputs reduces power consumption.
摘要翻译：并行乘法器由AND门的收缩阵列和分阶段组合的全加法器组成，使得每个阶段生成部分乘积，将其添加到先前的部分乘积，并将总和提供给下一阶段。提供了一种控制电路，其禁用阵列的每个级的输出，直到特定级的操作完成。输出禁用可以降低功耗。

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