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1. 发明授权

US06661294B2 Phase-locked loop circuit 失效
标题翻译：锁相环电路
公开(公告)号：US06661294B2
公开(公告)日：2003-12-09
申请号：US10122307
申请日：2002-04-16
申请人： Hisae Terashima , Hiroyuki Ueda
发明人： Hisae Terashima , Hiroyuki Ueda
IPC分类号： H03L700
CPC分类号： H03L7/14 , H03L7/148 , H03L7/199
摘要： A phase error signal indicating a most recent phase difference between an input clock signal and a feed-back signal is produced in a phase comparing unit. Also, the phase difference of the phase error signal is monitored in an abnormal condition detecting unit. When the phase difference is higher than a threshold value, the abnormal condition detecting unit judges that the input clock signal is set in an abnormal condition, and a frequency-controlled clock signal is produced in the voltage controlled oscillator according to the phase error signal. Therefore, the oscillation clock signal can be output without changing a phase of the oscillation clock signal while suppressing wonders or jitters.
摘要翻译：在相位比较单元中产生指示输入时钟信号和反馈信号之间的最近相位差的相位误差信号。此外，在异常状态检测单元中监视相位误差信号的相位差。当相位差高于阈值时，异常状态检测单元判断输入时钟信号被设置为异常状态，并且根据相位误差信号在压控振荡器中产生频率控制的时钟信号。因此，可以在不改变振荡时钟信号的相位的同时输出振荡时钟信号，同时抑制奇迹或抖动。

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