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1. 发明授权

US07373570B2 LSI device having scan separators provided in number reduced from signal lines of combinatorial circuits 有权
标题翻译：具有从组合电路的信号线减少的扫描分离器的LSI装置
公开(公告)号：US07373570B2
公开(公告)日：2008-05-13
申请号：US11305211
申请日：2005-12-19
申请人： Hiroyuki Hanamori , Kenji Asai , Hiroshi Yamasaki , Osamu Endoh
发明人： Hiroyuki Hanamori , Kenji Asai , Hiroshi Yamasaki , Osamu Endoh
IPC分类号： G01R31/28
CPC分类号： G01R31/31855
摘要： A scan separator in a large scale integration device is made more extensive to suppress an increase in the circuit scale of the entire device. In one embodiment, a scan separator is provided for every two signal lines interconnecting two combinatorial circuit blocks. Each scan separator includes a selector and a flip flop for constituting a scan path. Another selector is provided for selecting one of the two signal lines. As an input selector signal for the selector that selects one of the two signal lines, data for switching controlling are used, which are transferred from a test input terminal over the scan path and latched by the flip flop. The data for switching controlling are initially transferred over the scan path to each flip flop. The selector that selects one of the two signal lines is switched in accordance with the switching controlling data stored in the flip flop. The switching controlling data may be interchanged to select the either of the two signal lines.
摘要翻译：大规模集成装置中的扫描分离器被更广泛地抑制整个装置的电路规模的增加。在一个实施例中，为每两个互连两个组合电路块的信号线提供扫描分离器。每个扫描分离器包括用于构成扫描路径的选择器和触发器。提供另一选择器用于选择两条信号线之一。作为用于选择两条信号线之一的选择器的输入选择器信号，使用用于切换控制的数据，其从测试输入端子在扫描路径上传送并由触发器锁存。用于切换控制的数据最初通过扫描路径传送到每个触发器。根据存储在触发器中的切换控制数据来切换选择两条信号线之一的选择器。切换控制数据可以互换以选择两条信号线中的任一条。

2. 发明申请

US20060136796A1 LSI device having scan separators provided in number reduced from signal lines of combinatorial circuits 有权
标题翻译：具有从组合电路的信号线减少的扫描分离器的LSI装置
公开(公告)号：US20060136796A1
公开(公告)日：2006-06-22
申请号：US11305211
申请日：2005-12-19
申请人： Hiroyuki Hanamori , Kenji Asai , Hiroshi Yamasaki , Osamu Endoh
发明人： Hiroyuki Hanamori , Kenji Asai , Hiroshi Yamasaki , Osamu Endoh
IPC分类号： G01R31/28
CPC分类号： G01R31/31855
摘要： A scan separator in a large scale integration device is made intensive to suppress the circuit scale of the entire device from increasing. A scan separator is provided for every two signal lines interconnecting two combinatorial circuit blocks. Each scan separator includes one selector, a flip flop for constituting a scan path, and another selector for selecting one of the two signal lines. As an input selector signal for the other selector, data for switching controlling are used, which are transferred from a test input terminal over the scan path and latched by the flip flop. The data for switching controlling are initially transferred over the scan path to each flip flop. The other selector is switched in accordance with the switching controlling data stored in the flip flop to select one of the two signal lines. The switching controlling data may be interchanged to select the other signal line.
摘要翻译：大规模集成装置中的扫描分离器被强化以抑制整个装置的电路规模增加。为每两个互连两个组合电路块的信号线提供扫描分离器。每个扫描分离器包括一个选择器，用于构成扫描路径的触发器，以及用于选择两个信号线之一的另一个选择器。作为另一个选择器的输入选择器信号，使用用于切换控制的数据，其从测试输入端子在扫描路径上传送并由触发器锁存。用于切换控制的数据最初通过扫描路径传送到每个触发器。根据存储在触发器中的切换控制数据来切换另一个选择器，以选择两条信号线之一。切换控制数据可以互换以选择另一条信号线。

3. 发明授权

US07013404B2 Semiconductor integrated circuit characterized by timing adjustment of clock switching control 失效
标题翻译：半导体集成电路的特点是时钟切换控制的定时调整
公开(公告)号：US07013404B2
公开(公告)日：2006-03-14
申请号：US10259756
申请日：2002-09-30
申请人： Hiroyuki Hanamori
发明人： Hiroyuki Hanamori
IPC分类号： G06F1/08 , G06F1/12
CPC分类号： G06F1/08
摘要： The semiconductor integrated circuit capable of reducing the length of time required for clock switching is provided. The semiconductor integrated circuit includes a clock generation control circuit which is provided with a register capable of writing and reading specific data, and generates a frequency divided clock by inputting a reference clock with the timing of a clock frequency division setting signal. A clock control circuit constituting this semiconductor integrated circuit comprises a status shift circuit that controls clock frequency division/switching, a switching timing generation circuit that measures the timing with which a clock switch is made and a selection switching circuit that makes a switch between the reference clock and the frequency divided clock.
摘要翻译：提供了能够缩短时钟切换所需的时间长度的半导体集成电路。半导体集成电路包括具有能够写入和读取特定数据的寄存器的时钟产生控制电路，并且通过用时钟分频设置信号的定时输入基准时钟来产生分频时钟。构成该半导体集成电路的时钟控制电路包括控制时钟分频/切换的状态移位电路，测量进行时钟切换的定时的切换定时产生电路和在参考电路之间进行切换的选择切换电路时钟和分频时钟。

4. 发明授权

US07546481B2 Clock control circuit that generates and selects one of a divided clock signal and a multiplied clock signal as a bus clock signal 有权
标题翻译：时钟控制电路，其产生并选择分频时钟信号和倍增时钟信号中的一个作为总线时钟信号
公开(公告)号：US07546481B2
公开(公告)日：2009-06-09
申请号：US11368417
申请日：2006-03-07
申请人： Hiroyuki Hanamori
发明人： Hiroyuki Hanamori
IPC分类号： G06F1/04 , G06F1/08
CPC分类号： G06F1/06
摘要： A clock control circuit including a divider unit for dividing a master clock signal at a falling timing of the same to generate a divided clock signal, a multiplier unit for multiplying the master signal by n at a rising timing of the same, and thinning out an n-th clock pulse to generate a multiplied clock signal, and a selector unit for selecting a bus clock signal from multiplied clock signals at a variety of timings, derived from the multiplied clock signal, and the divided clock signal in accordance with a selection signal, and supplying the selected signal to a processor.
摘要翻译：一种时钟控制电路，包括：分频器单元，用于在其下降定时将主时钟信号分频以产生分频时钟信号;乘法器单元，用于在其上升时刻将主信号乘以n; 第n个时钟脉冲以产生相乘的时钟信号;以及选择器单元，用于根据乘法时钟信号从多个时钟信号中选择总线时钟信号，并根据选择信号选择分频时钟信号，并将所选择的信号提供给处理器。

5. 发明申请

US20060242446A1 Clock control circuit 有权
标题翻译：时钟控制电路
公开(公告)号：US20060242446A1
公开(公告)日：2006-10-26
申请号：US11368417
申请日：2006-03-07
申请人： Hiroyuki Hanamori
发明人： Hiroyuki Hanamori
IPC分类号： G06F1/00
CPC分类号： G06F1/06
摘要： A clock control circuit including a divider unit for dividing a master clock signal at a falling timing of the same to generate a divided clock signal, a multiplier unit for multiplying the master signal by n at a rising timing of the same, and thinning out an n-th clock pulse to generate a multiplied clock signal, and a selector unit for selecting a bus clock signal from multiplied clock signals at a variety of timings, derived from the multiplied clock signal, and the divided clock signal in accordance with a selection signal, and supplying the selected signal to a processor.
摘要翻译：一种时钟控制电路，包括：分频器单元，用于在其下降定时将主时钟信号分频以产生分频时钟信号;乘法器单元，用于在其上升时刻将主信号乘以n; 第n个时钟脉冲以产生相乘的时钟信号;以及选择器单元，用于根据乘法时钟信号从多个时钟信号中选择总线时钟信号，并根据选择信号选择分频时钟信号，并将所选择的信号提供给处理器。

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