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1. 发明申请

US20120105679A1 SEMICONDUCTOR INTEGRATED CIRCUIT AND MULTI-ANGLE VIDEO SYSTEM 有权
标题翻译：半导体集成电路和多角度视频系统
公开(公告)号：US20120105679A1
公开(公告)日：2012-05-03
申请号：US13274324
申请日：2011-10-15
申请人： Hiroshi OSUGA , Takaaki Suzuki , Atsushi Kiuchi , Kazuhide Kawade , Hiroyuki Hamasaki
发明人： Hiroshi OSUGA , Takaaki Suzuki , Atsushi Kiuchi , Kazuhide Kawade , Hiroyuki Hamasaki
IPC分类号： H04N5/217 , H04N5/76
CPC分类号： G06T5/006 , G06T2200/28 , G06T2207/10004 , H04N5/2173 , H04N5/23238 , H04N5/247 , H04N5/357 , H04N5/3572 , H04N5/77 , H04N5/907
摘要： The present invention is provided to lessen load on a bus in the case of storing image data captured by a plurality of cameras into a semiconductor memory. To a semiconductor integrated circuit, a plurality of cameras and a semiconductor memory can be coupled. The semiconductor integrated circuit includes a plurality of first interfaces, a second interface, a bus, and a plurality of image processing modules. The image processing modules include a process of performing distortion correction on image data in a pre-designated region, and writing the image data in the region subjected to the distortion correction into the semiconductor memory via the bus and the second interface. By excluding image data out of the pre-designated region from an object of distortion correction in the image processing modules, the amount of image data transferred to the semiconductor memory is reduced.
摘要翻译：提供本发明以在将由多个摄像机捕获的图像数据存储到半导体存储器的情况下减少总线上的负载。对于半导体集成电路，可以耦合多个摄像机和半导体存储器。半导体集成电路包括多个第一接口，第二接口，总线和多个图像处理模块。图像处理模块包括对预先指定区域中的图像数据进行失真校正的处理，并且经过失真校正的区域中的图像数据经由总线和第二接口写入半导体存储器。通过从图像处理模块中的失真校正对象中排除预先指定区域之外的图像数据，减少了传送到半导体存储器的图像数据量。

2. 发明申请

US20110314323A1 SEMICONDUCTOR DEVICE AND DATA PROCESSOR 有权
标题翻译：半导体器件和数据处理器
公开(公告)号：US20110314323A1
公开(公告)日：2011-12-22
申请号：US13220747
申请日：2011-08-30
申请人： Yoshihiko HOTTA , Seiichi SAITO , Hiroyuki HAMASAKI , Hirotaka HARA , Itaru NONOMURA
发明人： Yoshihiko HOTTA , Seiichi SAITO , Hiroyuki HAMASAKI , Hirotaka HARA , Itaru NONOMURA
IPC分类号： G06F1/12
CPC分类号： G06F1/3253 , G06F1/3237 , Y02D10/128 , Y02D10/151
摘要： To improve the speed of accessing a low-speed circuit block from a high-speed circuit block without significantly increasing power consumption.In a data processor having a bus controller that performs timing control of access from the CPU operated in synchronization with a high-speed first clock signal to a peripheral circuit operated in synchronization with a low-speed second clock signal, a timing control circuit is provided between the peripheral circuit and the bus controller, and the bus controller causes, in response to a read instruction from the peripheral circuit, the timing control circuit to output data held by the peripheral circuit to the bus controller in synchronization with the cycle of the high-speed clock signal, causes the timing control circuit to start, in response to a write instruction directed to the peripheral circuit, writing into the peripheral circuit in synchronization with the cycle of the high-speed clock signal, and terminates the writing in synchronization with the cycle of the low-speed clock signal.
摘要翻译：提高从高速电路块访问低速电路块的速度，而不会显着增加功耗。在具有总线控制器的数据处理器中，总线控制器执行与高速第一时钟信号同步操作的CPU的访问定时控制到与低速第二时钟信号同步操作的外围电路，提供定时控制电路在外围电路和总线控制器之间，并且总线控制器响应于来自外围电路的读取指令而导致定时控制电路将周边电路保持的数据与高速的周期同步地传送到总线控制器速度时钟信号，使定时控制电路响应于指向外围电路的写指令而启动，与高速时钟信号的周期同步地写入外围电路，并且与低速时钟信号的周期。

3. 发明申请

US20100182848A1 SEMICONDUCTOR DEVICE AND DATA PROCESSOR 有权
标题翻译：半导体器件和数据处理器
公开(公告)号：US20100182848A1
公开(公告)日：2010-07-22
申请号：US12636528
申请日：2009-12-11
申请人： Yoshihiko Hotta , Seiichi Saito , Hiroyuki Hamasaki , Hirotaka Hara , Itaru Nonomura
发明人： Yoshihiko Hotta , Seiichi Saito , Hiroyuki Hamasaki , Hirotaka Hara , Itaru Nonomura
IPC分类号： G11C7/10 , H03L7/00 , H03K17/00
CPC分类号： G06F1/3253 , G06F1/3237 , Y02D10/128 , Y02D10/151
摘要： To improve the speed of accessing a low-speed circuit block from a high-speed circuit block without significantly increasing power consumption.Ina data processor having a bus controller that performs timing control of access from the CPU operated in synchronization with a high-speed first clock signal to a peripheral circuit operated in synchronization with a low-speed second clock signal, a timing control circuit is provided between the peripheral circuit and the bus controller, and the bus controller causes, in response to a read instruction from the peripheral circuit, the timing control circuit to output data held by the peripheral circuit to the bus controller in synchronization with the cycle of the high-speed clock signal, causes the timing control circuit to start, in response to a write instruction directed to the peripheral circuit, writing into the peripheral circuit in synchronization with the cycle of the high-speed clock signal, and terminates the writing in synchronization with the cycle of the low-speed clock signal.
摘要翻译：提高从高速电路块访问低速电路块的速度，而不会显着增加功耗。 Ina数据处理器具有总线控制器，其执行与高速第一时钟信号同步操作的CPU的访问定时控制到与低速第二时钟信号同步操作的外围电路，定时控制电路设置在外围电路和总线控制器以及总线控制器响应于来自外围电路的读取指令，使定时控制电路与外围电路的高周期同步地将外围电路保持的数据输出到总线控制器，响应于针对外围电路的写入指令，使定时控制电路开始与高速时钟信号的周期同步地写入外围电路，并且与该时钟信号同步地终止写入周期的低速时钟信号。

4. 发明授权

US09367315B2 Image processing semiconductor device and image processing device 有权
标题翻译：图像处理半导体器件和图像处理器件
公开(公告)号：US09367315B2
公开(公告)日：2016-06-14
申请号：US12917840
申请日：2010-11-02
申请人： Hideaki Kido , Shoji Muramatsu , Hiroyuki Hamasaki , Akihiro Yamamoto
发明人： Hideaki Kido , Shoji Muramatsu , Hiroyuki Hamasaki , Akihiro Yamamoto
IPC分类号： H04N7/18 , G06F9/30
CPC分类号： G06F3/0659 , G06F3/0604 , G06F3/0673 , G06F9/30087 , G06K9/00805
摘要： Provided is an image processing device capable of an image processing with using a general-purpose image processing hardware in accordance with video input without mediation of a CPU. The image processing device includes: a storage medium for storing an image data acquired by video inputting unit for acquiring video images; a CPU for a general processing; image processing unit for processing the image data stored in the storage medium; setting unit for determining a processing content of the image processing unit; a command list indicating an order of setting and activating the image processing unit; and command writing unit for setting and activating the image processing unit based on the command list in synchronization with input of the image data from the video inputting unit without mediation of the CPU.
摘要翻译：提供了一种图像处理装置，其能够根据视频输入而使用通用图像处理硬件进行图像处理，而无需中介CPU。该图像处理装置包括：存储介质，用于存储由用于获取视频图像的视频输入单元获取的图像数据; 用于一般处理的CPU; 图像处理单元，用于处理存储在存储介质中的图像数据; 设置单元，用于确定图像处理单元的处理内容; 指示设置和激活图像处理单元的顺序的命令列表; 以及命令写入单元，用于根据来自视频输入单元的图像数据的输入同步地基于命令列表设置和激活图像处理单元，而无需CPU的中介。

5. 发明授权

US08977071B2 Image converting device and image converting system 有权
标题翻译：图像转换装置和图像转换系统
公开(公告)号：US08977071B2
公开(公告)日：2015-03-10
申请号：US13185007
申请日：2011-07-18
申请人： Hideaki Kido , Shoji Muramatsu , Hiroyuki Hamasaki , Akihiro Yamamoto
发明人： Hideaki Kido , Shoji Muramatsu , Hiroyuki Hamasaki , Akihiro Yamamoto
IPC分类号： G06K9/36 , G06K9/32 , G09G5/00 , G09G5/02 , H04N11/20 , H04N7/01 , H04N5/44 , H04N9/74 , H04N3/223 , H04N1/46 , H04N1/393 , G06T3/00
CPC分类号： H04N5/247 , B60R1/00 , B60R2300/60 , G06T3/00 , G06T3/20 , G06T5/006 , G06T2207/10016 , G06T2207/20172 , G06T2207/30252 , H04N5/21 , H04N7/18
摘要： Means which enables image conversion in which a plurality of conversion results can be output without once saving all of video-image data, which has been input from image-pickup means, in a storage medium is provided. A single line memory having a plurality of lines is used while switching the role thereof for a reading use by a video-image converting means and a use for inputting image data from the image-pickup means. The image converting means obtains an input image, which is in the line memory, and carries out conversion of the input image based on a conversion specifying means interpreted by an instruction decoder.
摘要翻译：提供了一种使得能够输出多个转换结果的图像转换的装置，而不会将从图像拾取装置输入的所有视频图像数据一次存储在存储介质中。使用具有多行的单行存储器，同时切换其角色以供视频图像转换装置的读取使用，以及用于从图像拾取装置输入图像数据的用途。图像转换装置获得在行存储器中的输入图像，并且基于由指令解码器解释的转换指定装置来执行输入图像的转换。

6. 发明授权

US08239600B2 Data processing system with selectable interrupt control 失效
标题翻译：具有可选中断控制的数据处理系统
公开(公告)号：US08239600B2
公开(公告)日：2012-08-07
申请号：US12558508
申请日：2009-09-12
申请人： Akihiro Yamamoto , Yasuhiko Hoshi , Hiroyuki Hamasaki
发明人： Akihiro Yamamoto , Yasuhiko Hoshi , Hiroyuki Hamasaki
IPC分类号： G06F13/26
CPC分类号： G06F13/24
摘要： The present invention provides a data processing system having excellent immediacy of interrupting process. Different interrupt request signals are supplied from a circuit module which can be commonly used by a plurality of central processing units to a plurality of interrupt controllers assigned to central processing units, respectively. In response to the input interrupt request signal, each of the interrupt controllers notifies the corresponding central processing unit of an interrupt. The circuit module selects an interrupt controller for supplying an interrupt request signal from the plural interrupt controllers. For example, the circuit module identifies a central processing unit which instructed a start request and supplies an interrupt request signal to an interrupt controller corresponding to the central processing unit. The burden of the interrupting process of the single central processing unit can be lessened. In addition, since the interrupting process in the single central processing unit is not necessary, interruption response of another central processing unit is increased.
摘要翻译：本发明提供一种具有优异的中断处理的数据处理系统。不同的中断请求信号从可以由多个中央处理单元共同使用的电路模块分别提供给分配给中央处理单元的多个中断控制器。响应于输入中断请求信号，每个中断控制器通知相应的中央处理单元一个中断。电路模块从多个中断控制器中选择中断控制器来提供中断请求信号。例如，电路模块识别指示开始请求的中央处理单元，并向与中央处理单元相对应的中断控制器提供中断请求信号。可以减轻单个中央处理单元的中断处理的负担。此外，由于不需要单个中央处理单元的中断处理，所以增加了另一个中央处理单元的中断响应。

7. 发明授权

US07868892B2 Data processor and graphic data processing device 有权
标题翻译：数据处理器和图形数据处理设备
公开(公告)号：US07868892B2
公开(公告)日：2011-01-11
申请号：US12237112
申请日：2008-09-24
申请人： Hirotaka Hara , Hiroyuki Hamasaki , Mitsuhiro Saeki , Kazuhiro Hirade , Makoto Takano
发明人： Hirotaka Hara , Hiroyuki Hamasaki , Mitsuhiro Saeki , Kazuhiro Hirade , Makoto Takano
IPC分类号： G06F13/14 , G06F13/36
CPC分类号： G06T11/203 , G06T1/20
摘要： An object of the present invention is to improve efficiency of transfer of control information, graphic data, and the like for drawing and display control in a graphic data processor. A graphic data processor includes: a CPU; a first bus coupled to the CPU; a DMAC for controlling a data transfer using the first bus; a bus bridge circuit for transmitting/receiving data to/from the first bus; a three-dimensional graphics module for receiving a command from the CPU via the first bus and performing a three-dimensional graphic process; a second bus coupled to the bus bridge circuit and a plurality of first circuit modules; a third bus coupled to the bus bridge circuit and second circuit modules; and a memory interface circuit coupled to the first and second buses and the three-dimensional graphic module and connectable to an external memory, wherein the bus bridge circuit can control a direct memory access transfer between an external circuit and the second bus.
摘要翻译：本发明的一个目的是提高图形数据处理器中用于绘制和显示控制的控制信息，图形数据等的传送效率。图形数据处理器包括：CPU; 耦合到CPU的第一个总线; 用于使用第一总线控制数据传输的DMAC; 用于向/从第一总线发送/接收数据的总线桥电路; 三维图形模块，用于经由第一总线从CPU接收命令并执行三维图形处理; 耦合到总线桥电路的第二总线和多个第一电路模块; 耦合到总线桥电路和第二电路模块的第三总线; 以及耦合到第一和第二总线和三维图形模块并且可连接到外部存储器的存储器接口电路，其中总线桥电路可以控制外部电路和第二总线之间的直接存储器访问传输。

8. 发明申请

US20100199283A1 DATA PROCESSING UNIT 审中-公开
标题翻译：数据处理单元
公开(公告)号：US20100199283A1
公开(公告)日：2010-08-05
申请号：US12698246
申请日：2010-02-02
申请人： Hideaki KIDO , Shoji MURAMATSU , Yasuhiko HOSHI , Hiroyuki HAMASAKI
发明人： Hideaki KIDO , Shoji MURAMATSU , Yasuhiko HOSHI , Hiroyuki HAMASAKI
IPC分类号： G06F9/48 , G06F9/50 , G06F13/24
CPC分类号： G06F9/5027 , G06F9/4812 , G06F9/485 , G06F2209/5021
摘要： When a CPU is processing a first task by using an accelerator for use in image processing, if a request for allocating the accelerator to a process of a second task is issued, the CPU sets an interruption flag when the process of the second task is prioritized over a process of the first task, and the accelerator is allowed to be used for the process of the second task when a state in which the interruption flag is set is detected at a timing predetermined in accordance with a process stage of the accelerator for the first task. Since the timing of detecting the set interruption flag is determined in accordance with a progress state of the process of the task to be interrupted, task switching can be made at a timing of reducing overhead for save and return for the process of the task to be interrupted.
摘要翻译：当CPU通过使用用于图像处理的加速器来处理第一任务时，如果发出向第二任务的处理分配加速器的请求，则当第二任务的处理被优先化时，CPU设置中断标志通过第一任务的处理，并且当在根据预定的加速器的处理阶段预定的定时检测到设置了中断标志的状态时，加速器被允许用于第二任务的处理。第一任务由于根据待中断的任务的进程的状态确定检测到设定的中断标志的定时，所以可以在减少任务的处理的保存和返回的开销的时刻进行任务切换中断了

9. 发明申请

US20100088493A1 IMAGE PROCESSING DEVICE AND DATA PROCESSOR 审中-公开
标题翻译：图像处理设备和数据处理器
公开(公告)号：US20100088493A1
公开(公告)日：2010-04-08
申请号：US12566123
申请日：2009-09-24
申请人： Yoshitaka TAKAHASHI , Shoji MURAMATSU , Tetsuaki NAKAMIKAWA , Hiroyuki HAMASAKI , So OTSUKA
发明人： Yoshitaka TAKAHASHI , Shoji MURAMATSU , Tetsuaki NAKAMIKAWA , Hiroyuki HAMASAKI , So OTSUKA
IPC分类号： G06F9/302 , G06F12/00
CPC分类号： G06F9/3001 , G06F9/30101 , G06T1/00
摘要： A restriction is given to the calculation function for image processing achieved by the hard-wired system and the memory access control of a buffer memory, and a range of the restriction is made variable by a program control and others. Data is inputted to the buffer memory from the outside with a restriction of “in units of memory line”, and the number of memory lines and positions of the same to which data is inputted can be programmable by the control circuit. The arithmetic circuit is subjected to the restriction of performing the calculation in units of data of one or plural memory lines supplied from the buffer memory, and a calculation processing content in units of calculation processing for the units of data can be programmably assigned by the control circuit.
摘要翻译：对由硬接线系统和缓冲存储器的存储器访问控制实现的图像处理的计算功能进行限制，并且通过程序控制等来限制范围变化。数据以“以存储线为单位”的限制从外部输入到缓冲存储器，并且通过控制电路可编程输入数据的存储器线数和位置数。算术电路受到以缓冲存储器提供的一个或多个存储器线的数据为单位执行计算的限制，并且可以通过控制来可编程地分配用于数据单元的计算处理单位的计算处理内容电路。

10. 发明申请

US20050030311A1 Data processor and graphic data processing device 有权
标题翻译：数据处理器和图形数据处理设备
公开(公告)号：US20050030311A1
公开(公告)日：2005-02-10
申请号：US10891047
申请日：2004-07-15
申请人： Hirotaka Hara , Hiroyuki Hamasaki , Mitsuhiro Saeki , Kazuhiro Hirade , Makoto Takano
发明人： Hirotaka Hara , Hiroyuki Hamasaki , Mitsuhiro Saeki , Kazuhiro Hirade , Makoto Takano
IPC分类号： G06F13/28 , G06F15/78 , G06T1/20 , G06T11/20 , G06T11/40 , G06T15/00 , G06T1/00 , G06F13/14
CPC分类号： G06T11/203 , G06T1/20
摘要： An object of the present invention is to improve efficiency of transfer of control information, graphic data, and the like for drawing and display control in a graphic data processor. A graphic data processor includes: a CPU; a first bus coupled to the CPU; a DMAC for controlling a data transfer using the first bus; a bus bridge circuit for transmitting/receiving data to/from the first bus; a three-dimensional graphics module for receiving a command from the CPU via the first bus and performing a three-dimensional graphic process; a second bus coupled to the bus bridge circuit and a plurality of first circuit modules; a third bus coupled to the bus bridge circuit and second circuit modules; and a memory interface circuit coupled to the first and second buses and the three-dimensional graphic module and connectable to an external memory, wherein the bus bridge circuit can control a direct memory access transfer between an external circuit and the second bus.
摘要翻译：本发明的一个目的是提高图形数据处理器中绘图和显示控制的控制信息，图形数据等的传送效率。图形数据处理器包括：CPU; 耦合到CPU的第一个总线; 用于使用第一总线控制数据传输的DMAC; 用于向/从第一总线发送/接收数据的总线桥电路; 三维图形模块，用于经由第一总线从CPU接收命令并执行三维图形处理; 耦合到总线桥电路的第二总线和多个第一电路模块; 耦合到总线桥电路和第二电路模块的第三总线; 以及耦合到第一和第二总线和三维图形模块并且可连接到外部存储器的存储器接口电路，其中总线桥电路可以控制外部电路和第二总线之间的直接存储器访问传输。

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