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1. 发明授权

US09034774B2 Film forming method using plasma 有权
标题翻译：使用等离子体的成膜方法
公开(公告)号：US09034774B2
公开(公告)日：2015-05-19
申请号：US14113134
申请日：2012-04-23
申请人： Kouji Tanaka , Hirokazu Ueda
发明人： Kouji Tanaka , Hirokazu Ueda
IPC分类号： H01L21/31 , H01L21/316 , C23C16/34 , C23C16/455 , C23C16/511 , H01L21/02 , H01L21/318
CPC分类号： H01L21/316 , C23C16/345 , C23C16/4554 , C23C16/511 , H01L21/02164 , H01L21/0217 , H01L21/02211 , H01L21/02274 , H01L21/0228 , H01L21/318
摘要： This film forming method comprises: a first material gas supply step (A) wherein a first raw material gas is supplied over the substrate to be processed so that a first chemical adsorption layer, which is adsorbed on the substrate by means of the first raw material gas is formed on the substrate to be processed, a second material gas supply step (C) wherein a second raw material that is different from the first raw material gas is supplied over the substrate, on which the first chemical adsorption layer has been formed, so that a second chemical adsorption layer, which is adsorbed by means of the second raw material gas, is formed on the first chemical adsorption layer; and a plasma processing step (E) wherein a plasma processing is carried on at least the first and second chemical adsorption layers using microwave plasma.
摘要翻译：该成膜方法包括：第一原料气体供给工序（A），其中第一原料气体供给到被处理基板上，使得通过第一原料吸附在基板上的第一化学吸附层在被处理基板上形成气体，在其上形成有第一化学吸附层的基板上供给与第一原料气体不同的第二原料的第二原料气体供给工序（C）使得通过第二原料气体吸附的第二化学吸附层形成在第一化学吸附层上; 和等离子体处理步骤（E），其中至少使用微波等离子体对第一和第二化学吸附层进行等离子体处理。

2. 发明申请

US20140227458A1 PLASMA EVALUATION METHOD, PLASMA PROCESSING METHOD AND PLASMA PROCESSING APPARATUS 审中-公开
标题翻译：等离子体评估方法，等离子体处理方法和等离子体处理装置
公开(公告)号：US20140227458A1
公开(公告)日：2014-08-14
申请号：US14112172
申请日：2012-04-18
申请人： Takayuki Karakawa , Hirokazu Ueda
发明人： Takayuki Karakawa , Hirokazu Ueda
IPC分类号： G01J3/443 , C23C16/50 , C23C16/52
CPC分类号： G01J3/443 , C23C16/34 , C23C16/45536 , C23C16/50 , C23C16/52 , G01J2003/4435 , H01J37/32972 , H01L21/0217 , H01L21/02274 , H01L21/0228 , H01L21/31111
摘要： Disclosed is a plasma evaluation method that evaluates plasma P that forms a nitride film by an atomic layer deposition method. First, light emission from the plasma P generated from a gas G that contains nitrogen atoms and hydrogen atoms is detected. Then, evaluation of the plasma P is performed by using a result of comparing an intensity ratio between a first peak caused by hydrogen atoms and a second peak different from the first peak and caused by hydrogen atoms in an intensity spectrum of the detected light emission with a reference value calculated in advance from a relationship between the intensity ratio and an indicator that indicates a film quality of the nitride film.
摘要翻译：公开了通过原子层沉积法评价形成氮化物膜的等离子体P的等离子体评价方法。首先，检测从含有氮原子和氢原子的气体G产生的等离子体P的发光。然后，使用比较由氢原子引起的第一峰与第一峰不同的第二峰与由检测出的发光的强度谱中的氢原子引起的强度比的结果来进行等离子体P的评价，从强度比与表示氮化膜的膜质量的指标之间的关系预先计算出的基准值。

3. 发明申请

US20120190211A1 FILM FORMING METHOD, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, INSULATING FILM AND SEMICONDUCTOR DEVICE 审中-公开
标题翻译：薄膜成型方法，半导体器件制造方法，绝缘膜和半导体器件
公开(公告)号：US20120190211A1
公开(公告)日：2012-07-26
申请号：US13496563
申请日：2010-09-09
申请人： Hirokazu Ueda , Yusuke Ohsawa , Masahiro Horigome
发明人： Hirokazu Ueda , Yusuke Ohsawa , Masahiro Horigome
IPC分类号： H01L21/31 , H01L21/30
CPC分类号： C23C16/401 , C23C16/345 , C23C16/45542 , H01L21/02164 , H01L21/0217 , H01L21/02274 , H01L21/0228 , H01L21/28194 , H01L29/66181
摘要： In a film forming method, firstly, a processing target substrate W as a base of a semiconductor device is held on a mounting table 34 by an electrostatic chuck. Then, a film forming gas is adsorbed onto the processing target substrate W (a gas adsorption process) ((A) of FIG. 6). Thereafter, the inside of the processing chamber 32 is evacuated in order to remove residues of the film forming gas ((B) of FIG. 6). Upon the completion of the first exhaust process, a plasma process using microwave is performed ((C) of FIG. 6). Upon the completion of the plasma process, the inside of the processing chamber 32 is evacuated in order to remove an unreacted reactant gas and the like ((D) of FIG. 6). These series of steps (A) to (D) are repeated in this sequence until a desired film thickness is obtained.
摘要翻译：在成膜方法中，首先，作为半导体装置的基底的处理对象基板W由静电卡盘保持在安装台34上。然后，成膜气体被吸附到处理对象基板W（气体吸附工序）（图6的（A））上。此后，为了除去成膜气体的残留物（图6的（B）），处理室32的内部被抽真空。在第一排气处理完成时，进行使用微波的等离子体处理（图6的（C））。在完成等离子体处理之后，为了除去未反应的反应气体等（图6的（D）），将处理室32的内部抽真空。以该顺序重复这些一系列步骤（A）至（D），直至获得所需的膜厚度。

4. 发明授权

US07366051B2 Word line driver circuitry and methods for using the same 有权
标题翻译：字线驱动电路及使用方法
公开(公告)号：US07366051B2
公开(公告)日：2008-04-29
申请号：US11472107
申请日：2006-06-20
申请人： Hirokazu Ueda
发明人： Hirokazu Ueda
IPC分类号： G11C8/00 , G11C5/06 , G11C7/00
CPC分类号： G11C8/08 , G11C11/4085 , G11C11/413
摘要： Word line driver circuitry for selectively charging and discharging one or more word lines is provided. The driver circuitry uses a dual transistor topology, where a first transistor is driven by a signal, DOUT, and a second transistor is driven by a time-delayed complement of the DOUT, DOUT_BAR. The time delay prevents DOUT_BAR from changing its state immediately after DOUT changes state. As result, both the first and second transistors are turned ON at the same time for a predetermined of time. It is during this time that the voltage on the word line is rapidly driven to a LOW voltage. When the second transistor turns OFF, high impedance circuitry limits the flow of leakage current. This minimizes leakage current when the word line is OFF and when short circuit conditions are present between two or more word lines or between a word line and a bit line.
摘要翻译：提供用于选择性地对一个或多个字线进行充电和放电的字线驱动器电路。驱动器电路使用双晶体管拓扑，其中第一晶体管由信号DOUT驱动，并且第二晶体管由DOUT DOUT_BAR的时间延迟的补码驱动。时间延迟可防止DOUT_BAR在DOUT更改状态后立即更改其状态。结果，第一和第二晶体管同时接通预定的时间。在这段时间内，字线上的电压被快速驱动到低电压。当第二个晶体管关断时，高阻抗电路会限制漏电流。当字线为OFF并且在两条或多条字线之间或字线与位线之间存在短路状况时，这将使漏电流最小化。

5. 发明授权

US07268402B2 Memory cell with trench-isolated transistor including first and second isolation trenches 有权
标题翻译：具有沟槽隔离晶体管的存储单元包括第一和第二隔离沟槽
公开(公告)号：US07268402B2
公开(公告)日：2007-09-11
申请号：US11119128
申请日：2005-04-29
申请人： Keiji Jono , Hirokazu Ueda , Hiroyuki Watanabe
发明人： Keiji Jono , Hirokazu Ueda , Hiroyuki Watanabe
IPC分类号： H01L21/762
CPC分类号： H01L21/76232 , H01L27/10873
摘要： An isolation trench in a semiconductor includes a first isolation trench portion having a first depth and having a first sidewall intersecting a surface of the semiconductor at a first angle. A second isolation trench portion extends within and below the first isolation trench portion. The second isolation trench portion has a second depth and includes a second sidewall. The second sidewall intersects the first sidewall at an angle with respect to the surface that is greater than the first angle. A dielectric material fills the first and second isolation trench portions.
摘要翻译：半导体中的隔离沟槽包括具有第一深度并且具有以第一角度与半导体的表面相交的第一侧壁的第一隔离沟槽部分。第二隔离沟槽部分在第一隔离沟槽部分内和下方延伸。第二隔离沟槽部分具有第二深度并且包括第二侧壁。第二侧壁相对于大于第一角度的表面成一定角度与第一侧壁相交。电介质材料填充第一和第二隔离沟槽部分。

6. 发明申请

US20050122792A1 Method and apparatus for enhanced sensing of low voltage memory 有权
标题翻译：用于增强低电压记忆感测的方法和装置
公开(公告)号：US20050122792A1
公开(公告)日：2005-06-09
申请号：US11038400
申请日：2005-01-19
申请人： Hirokazu Ueda
发明人： Hirokazu Ueda
IPC分类号： G11C11/409 , G11C7/06 , G11C7/00
CPC分类号： G11C7/065 , G11C2207/065
摘要： A differential sensing circuit and sensing method for use in a low voltage memory device. The sensing circuit includes a cross-coupled sensing circuit for coupling with a memory element, a pull-up circuit and a multistage pull-down circuit. The multistage pull-down circuit accelerates the latching process of the cross-coupled sensing circuit by briefly pulling the cross-coupled sensing circuit to a potential below ground in order to increase the gate potential differential on at least a portion of the transistors within the cross-coupled sensing circuit. Once the latching transitions have commenced at an acceptable rate, the below-ground potential is removed and the traditional logic level pull-up and ground-potential pull-down circuits are activated.
摘要翻译：一种用于低电压存储器件的差分感测电路和感测方法。感测电路包括用于与存储元件，上拉电路和多级下拉电路耦合的交叉耦合感测电路。多级下拉电路通过将交叉耦合的感测电路简单地拉到低于地电位的电位来加速交叉耦合感测电路的锁存过程，以便增加十字形内的晶体管的至少一部分上的栅极电位差耦合感测电路。一旦闭锁转换以可接受的速率开始，则地下电位被去除，传统的逻辑电平上拉电路和地电位下拉电路被激活。

7. 发明授权

US06830977B1 METHODS OF FORMING AN ISOLATION TRENCH IN A SEMICONDUCTOR, METHODS OF FORMING AN ISOLATION TRENCH IN A SURFACE OF A SILICON WAFER, METHODS OF FORMING AN ISOLATION TRENCH-ISOLATED TRANSISTOR, TRENCH-ISOLATED TRANSISTOR, TRENCH ISOLATION STRUCTURES FORMED IN A SEMICONDUCTOR, MEMORY CELLS AND DRAMS 有权
标题翻译：在半导体中形成隔离层的方法，在硅波表面形成隔离光束的方法，形成隔离光束隔离晶体管的方法，TRENCH隔离晶体管，在半导体，存储单元中形成的TRENCH隔离结构和 DRAMS
公开(公告)号：US06830977B1
公开(公告)日：2004-12-14
申请号：US09652550
申请日：2000-08-31
申请人： Keiji Jono , Hirokazu Ueda , Hiroyuki Watanabe
发明人： Keiji Jono , Hirokazu Ueda , Hiroyuki Watanabe
IPC分类号： H01L21336
CPC分类号： H01L21/76232 , H01L27/10873
摘要： A method of forming an isolation trench in a semiconductor includes forming a first isolation trench portion having a first depth and having a first sidewall intersecting a surface of the semiconductor at a first angle. The method also includes forming a second isolation trench portion within and extending below the first isolation trench portion. The second isolation trench portion has a second depth and includes a second sidewall. The second sidewall intersects the first sidewall at an angle with respect to the surface that is greater than the first angle. A dielectric material fills the first and second isolation trench portions.
摘要翻译：在半导体中形成隔离沟槽的方法包括：形成具有第一深度的第一隔离沟槽部分，并且具有以第一角度与半导体表面相交的第一侧壁。该方法还包括在第一隔离沟槽部分的内部并在其下延伸形成第二隔离沟槽部分。第二隔离沟槽部分具有第二深度并且包括第二侧壁。第二侧壁相对于大于第一角度的表面成一定角度与第一侧壁相交。电介质材料填充第一和第二隔离沟槽部分。

8. 发明授权

US5824158A Chemical vapor deposition using inductively coupled plasma and system therefor 失效
标题翻译：使用电感耦合等离子体的化学气相沉积及其系统
公开(公告)号：US5824158A
公开(公告)日：1998-10-20
申请号：US917803
申请日：1997-08-27
申请人： Koichiro Takeuchi , Hirokazu Ueda , Akira Narai
发明人： Koichiro Takeuchi , Hirokazu Ueda , Akira Narai
IPC分类号： C23C16/507 , H01J37/32 , C23C16/00
CPC分类号： H01J37/321 , C23C16/507
摘要： An ICP (Inductively Coupled Plasma) system is used as a plasma generating means. A CVD process gas is introduced within a vacuum vessel from a gas inlet nozzle, and is then converted into plasma by a high frequency electric field induced within the vacuum vessel by an electromagnetic wave from an antenna. A sample can be located at a position not to be exposed to plasma, and a decomposed product material produced from the CVD process gas by the plasma is deposited on the surface of the sample mounted on a sample stage, thus forming a film. A dielectric viewing port, the antenna and the sample are disposed along the same axial direction such that the directions of the planes thereof correspond to each other, so that the film formation on the surface of the sample within the vacuum vessel can be observed through the transparent dielectric viewing port. When a CVD process gas of a CVD source gas mixed with a rare gas is introduced in the vacuum vessel and a bias voltage is applied to the sample, the film is formed by the CVD source gas and it is simultaneously planarized by sputter etching by the rare gas. When an antenna serving as a target material is disposed within the vacuum vessel, it is possible to eliminate the cutoff of the high frequency power which, has been generated for the inductive coupling from the outside of the vacuum vessel.
摘要翻译：使用ICP（感应耦合等离子体）系统作为等离子体发生装置。将CVD工艺气体从气体入口喷嘴引入真空容器内，然后通过来自天线的电磁波在真空容器内感应的高频电场转换成等离子体。样品可以位于不暴露于等离子体的位置，并且通过等离子体由CVD处理气体产生的分解产物材料沉积在安装在样品台上的样品的表面上，从而形成膜。电介质观察口，天线和样品沿着相同的轴向方向设置，使得其平面的方向彼此对应，使得真空容器内的样品表面上的成膜可以通过透明电介质观察口。当将与稀有气体混合的CVD源气体的CVD工艺气体引入真空容器中并向样品施加偏置电压时，该膜由CVD源气体形成，并且通过溅射蚀刻同时被平坦化稀有气体当用作目标材料的天线设置在真空容器内时，可以消除从真空容器的外部产生的用于电感耦合的高频功率的截止。

9. 发明申请

US20110074013A1 FILM FORMING METHOD OF SILICON OXIDE FILM, SILICON OXIDE FILM, SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE 有权
标题翻译：硅氧烷膜，硅氧烷膜，半导体器件的薄膜形成方法和半导体器件的制造方法
公开(公告)号：US20110074013A1
公开(公告)日：2011-03-31
申请号：US12992209
申请日：2009-05-11
申请人： Hirokazu Ueda , Yoshinobu Tanaka , Yusuke Ohsawa , Toshihisa Nozawa , Takaaki Matsuoka
发明人： Hirokazu Ueda , Yoshinobu Tanaka , Yusuke Ohsawa , Toshihisa Nozawa , Takaaki Matsuoka
IPC分类号： H01L21/31 , C01B33/113 , H01L23/48
CPC分类号： H01L21/76224 , C23C16/402 , C23C16/511 , H01L21/02164 , H01L21/02274 , H01L21/28273 , H01L21/31612
摘要： A silicon compound gas, an oxidizing gas, and a rare gas are supplied into a chamber (2) of a plasma processing apparatus (1). A microwave is supplied into the chamber (2), and a silicon oxide film is formed on a target substrate with plasma generated by the microwave. A partial pressure ratio of the rare gas is 10% or more of a total gas pressure of the silicon compound gas, the oxidizing gas, and the rare gas, and an effective flow ratio of the silicon compound gas and the oxidizing gas (oxidizing gas/silicon compound gas) is not less than 3 but not more than 11.
摘要翻译：将硅化合物气体，氧化气体和稀有气体供给到等离子体处理装置（1）的室（2）中。微波供应到室（2）中，并且在目标衬底上用微波产生的等离子体形成氧化硅膜。稀有气体的分压比为硅化合物气体，氧化气体和稀有气体的总气体压力的10％以上，硅化合物气体和氧化气体的有效流量比（氧化气体 /硅化合物气体）不小于3但不大于11。

10. 发明授权

US5218330A Apparatus and method for easily adjusting the resonant frequency of a dielectric TEM resonator 失效
标题翻译：用于容易地调节电介质TEM谐振器的谐振频率的装置和方法
公开(公告)号：US5218330A
公开(公告)日：1993-06-08
申请号：US701112
申请日：1991-05-17
申请人： Kenzi Omiya , Hideo Sugawara , Hiroshi Suzuki , Hirokazu Ueda
发明人： Kenzi Omiya , Hideo Sugawara , Hiroshi Suzuki , Hirokazu Ueda
IPC分类号： H01P7/04
CPC分类号： H01P7/04
摘要： A dielectric TEM resonator, whose resonant frequency is adjustable in both directions after being incorporated in a circuit, is disclosed. A first dielectric TEM resonator comprises a metal member disposed near an open end of a resonator body and coupled to an inner or outer conductor of the resonator body. The resonant frequency is adjusted by adjusting a distance between the open end and the metal member. A dielectric material of a second dielectric TEM resonator is partially exposed, and a dielectric board for mounting the resonator body is also exposed in a corresponding part to the exposed part of the dielectric material. The exposed part of the dielectric board is partially covered with a metal plate. The resonant frequency is adjusted by adjusting the covered area.
摘要翻译：公开了一种电介质TEM谐振器，其谐振频率在并入电路之后在两个方向上可调节。第一电介质TEM谐振器包括设置在谐振器本体的开口端附近并耦合到谐振器本体的内导体或外导体的金属构件。通过调整开口端和金属构件之间的距离来调节谐振频率。第二电介质TEM谐振器的电介质材料被部分地暴露，并且用于安装谐振器体的电介质板也暴露在介电材料的暴露部分的对应部分中。电介质板的暴露部分被金属板部分覆盖。通过调整覆盖面积来调节谐振频率。

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