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1. 发明授权

US08664727B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US08664727B2
公开(公告)日：2014-03-04
申请号：US12613081
申请日：2009-11-05
申请人： Hirofumi Harada
发明人： Hirofumi Harada
IPC分类号： H01L27/088
CPC分类号： H01L21/823892 , H01L27/0207 , H01L27/0928
摘要： Provided is a semiconductor integrated circuit device capable of realizing an analog circuit required to have a high-precision relative ratio between adjacent transistors, which is reduced in size and cost. A single MOS transistor is provided within each of well regions. A plurality of the MOS transistors is combined to serve as an analog circuit block. Since distances between the well regions and channel regions may be made equal to one another, a high-precision semiconductor integrated circuit device can be obtained.
摘要翻译：提供了能够实现相邻晶体管之间具有高精度相对比例所需的模拟电路的半导体集成电路器件，其尺寸和成本降低。在每个阱区域内提供单个MOS晶体管。多个MOS晶体管组合起来用作模拟电路块。由于阱区域和沟道区域之间的距离可以彼此相等，所以可以获得高精度的半导体集成电路器件。

2. 发明授权

US08169052B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08169052B2
公开(公告)日：2012-05-01
申请号：US12328207
申请日：2008-12-04
申请人： Hirofumi Harada
发明人： Hirofumi Harada
IPC分类号： H01L29/72
CPC分类号： H01L29/8605 , H01L27/016 , H01L27/0802 , H01L27/1203
摘要： A metal electrode is disposed on each of a plurality of resistor groups which are made of polycrystalline silicon resistors and constitute a resistor circuit. The metal electrode is connected to an end of the resistor via another interconnecting layer. Accordingly, the external influence which the metal electrode receives during a semiconductor manufacturing process is prevented from directly acting on the resistor, whereby resistance variation is suppressed.
摘要翻译：金属电极设置在由多晶硅电阻器制成并构成电阻电路的多个电阻器组中的每一个上。金属电极通过另一个互连层连接到电阻器的一端。因此，防止了在半导体制造过程中金属电极接收的外部影响直接作用在电阻器上，从而抑制了电阻变化。

3. 发明授权

US06720633B2 High withstand voltage insulated gate N-channel field effect transistor 有权
标题翻译：高耐压绝缘栅N沟道场效应晶体管
公开(公告)号：US06720633B2
公开(公告)日：2004-04-13
申请号：US10306696
申请日：2002-11-27
申请人： Hirofumi Harada , Jun Osanai
发明人： Hirofumi Harada , Jun Osanai
IPC分类号： H01L2976
CPC分类号： H01L29/0847 , H01L29/0878 , H01L29/1033 , H01L29/1083 , H01L29/42368 , H01L29/66659 , H01L29/7835
摘要： A high withstand voltage insulated gate N-channel field effect transistor has N-type source and drain regions formed on a semiconductor substrate, and a channel forming region disposed between the source and drain regions. A gate insulating film is disposed over the channel forming region. A gate electrode is formed on the channel forming region through the gate insulating film. N-type low concentration regions are formed between respective ones of the drain region and the channel forming region and the source region and the channel forming region. Second insulating films are formed on respective ones of the low concentration regions. A P-type buried layer is formed in a boundary region between the semiconductor substrate and the epitaxial layer and below the source region, the drain region, the channel forming region, the gate insulating film, and the second insulating films. A P-type well layer is formed in a part of a region under the gate insulating film.
摘要翻译：高耐压绝缘栅N沟道场效应晶体管具有形成在半导体衬底上的N型源区和漏区，以及设置在源区和漏区之间的沟道形成区。栅极绝缘膜设置在沟道形成区域的上方。栅极电极通过栅极绝缘膜形成在沟道形成区域上。在漏极区域和沟道形成区域以及源极区域和沟道形成区域中的各个区域之间形成N型低浓度区域。在各个低浓度区域上形成第二绝缘膜。在半导体衬底和外延层之间并且在源极区域，漏极区域，沟道形成区域，栅极绝缘膜和第二绝缘膜之下的边界区域中形成P型掩埋层。 P型阱层形成在栅极绝缘膜下方的区域的一部分中。

4. 发明授权

US06511885B2 Vertical MOS transistor and method of manufacturing the same 有权
标题翻译：垂直MOS晶体管及其制造方法
公开(公告)号：US06511885B2
公开(公告)日：2003-01-28
申请号：US09767505
申请日：2001-01-23
申请人： Hirofumi Harada , Jun Osanai
发明人： Hirofumi Harada , Jun Osanai
IPC分类号： H01L21336
CPC分类号： H01L29/7813 , H01L29/1095 , H01L29/4232 , H01L29/42368 , H01L29/4238 , H01L29/781
摘要： There are provided a vertical MOS transistor in which a high frequency characteristic is improved by reducing a feedback capacitance, and a method of manufacturing the same. When a gate voltage is applied to a gate electrode, a channel is formed in a p− epitaxial growth layer along a trench, and an electron current flows from an n+ drain layer to the p− epitaxial growth layer. In this case, an overlapping area between a gate and the drain layer through a gate oxide film is smaller than prior art, and the capacitance between the gate and the drain layer is smaller than the prior art. Thus, the feedback capacitance becomes small and the high frequency characteristic is improved. Further, since a portion of the gate oxide film at the bottom of the trench is thicker than the portion at the side wall, the distance between the gate and the n+ semiconductor substrate becomes larger than the prior art, and the capacitance formed between the gate and the n+ semiconductor substrate is smaller than the prior art. Thus, the high frequency characteristic is improved as compared with the prior art.
摘要翻译：提供了通过降低反馈电容来提高高频特性的垂直MOS晶体管及其制造方法。当栅极电压施加到栅电极时，沿着沟槽在p外延生长层中形成沟道，并且电子电流从n +漏极层流到p-外延生长层。在这种情况下，通过栅极氧化膜的栅极和漏极层之间的重叠区域比现有技术小，并且栅极和漏极层之间的电容小于现有技术。因此，反馈电容变小，提高了高频特性。此外，由于沟槽底部的栅极氧化膜的一部分比侧壁的部分厚，所以栅极与n +半导体衬底之间的距离变得比现有技术大，并且栅极之间形成的电容并且n +半导体衬底比现有技术小。因此，与现有技术相比，高频特性得到改善。

5. 发明授权

US06426258B1 Method of manufacturing a semiconductor integrated circuit device 失效
标题翻译：制造半导体集成电路器件的方法
公开(公告)号：US06426258B1
公开(公告)日：2002-07-30
申请号：US09219997
申请日：1998-12-23
申请人： Hirofumi Harada , Jun Osanai
发明人： Hirofumi Harada , Jun Osanai
IPC分类号： H01L21336
CPC分类号： H01L29/66681 , H01L21/26586 , H01L29/0847 , H01L29/1095 , H01L29/66674 , H01L29/7816
摘要： A method of manufacturing a semiconductor integrated circuit device comprises forming a gate insulating film on a surface of a semiconductor substrate of a first conductivity type, forming a polycrystal silicon film on the gate insulating film, etching the polycrystal silicon film to form a gate electrode on a portion of the gate insulating film, etching the gate insulating film except at the portion thereof where the gate electrode has been formed, and forming a thermal oxide film on the semiconductor substrate at regions corresponding to the etched gate insulating film. Impurities of a second conductivity type are implanted into a source region in the semiconductor substrate through the thermal oxide film to form a body region of the second conductivity type. The semiconductor substrate is then heated at a temperature of 1000° C. or higher. Impurities of the first conductivity type are then implanted into the body region at an inclination angle equal to or greater than 7° with respect to a line perpendicular to the surface of the semiconductor substrate so that the impurities of the first conductivity type are implanted to a depth from the surface of the semiconductor substrate which is less than a depth of the source region from the surface of the semiconductor substrate.
摘要翻译：一种制造半导体集成电路器件的方法包括在第一导电类型的半导体衬底的表面上形成栅极绝缘膜，在栅极绝缘膜上形成多晶硅膜，蚀刻多晶硅膜以形成栅电极栅极绝缘膜的一部分，蚀刻除了形成有栅电极的部分以外的栅极绝缘膜，并且在与蚀刻的栅极绝缘膜对应的区域的半导体衬底上形成热氧化膜。通过热氧化膜将第二导电类型的杂质注入到半导体衬底的源极区域中以形成第二导电类型的体区。然后将半导体衬底在1000℃或更高的温度下加热。然后将第一导电类型的杂质以相对于半导体衬底的表面的线等于或大于7°的倾斜角度注入体区，使得第一导电类型的杂质被植入到从半导体衬底的表面的深度小于半导体衬底的表面的源极区的深度。

6. 发明授权

US6013940A Poly-crystalline silicon film ladder resistor 失效
标题翻译：多晶硅膜梯形电阻
公开(公告)号：US6013940A
公开(公告)日：2000-01-11
申请号：US516627
申请日：1995-08-18
申请人： Hirofumi Harada , Jun Osanai , Yoshikazu Kojima , Yutaka Saitoh
发明人： Hirofumi Harada , Jun Osanai , Yoshikazu Kojima , Yutaka Saitoh
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L27/06 , H01L27/08 , H01L29/00
CPC分类号： H01L28/20 , H01L27/0629 , H01L27/0802
摘要： A resistor ladder network may be formed with a reduced space on a semiconductor substrate by patterning a plurality of layers of resistive polycrystalline silicon films spaced by insulating layers. Such a device includes a first insulating film formed on a semiconductor substrate, one or more serial-connected first resistors formed in a first polycrystalline silicon film provided on the semiconductor substrate via the first insulating film, a second insulating film provided on the first polycrystalline silicon film, one or more series-connected second resistors formed in a second polycrystalline silicon film provided apart from the first polycrystalline silicon film via the second insulating film, the second polycrystalline silicon film being connected to the first polycrystalline silicon film. A third insulating film is provided over the second polycrystalline silicon film, and metal wires provided on a surface of the second polycrystalline silicon film via contact holes formed in the third insulating film. Preferably, the first polycrystalline silicon film is thicker than the second polycrystalline silicon film, the impurity concentration of the first polycrystalline silicon film is lower than the impurity concentration of the second polycrystalline silicon film, and the grain size of the first polycrystalline silicon film is smaller than that of the second polycrystalline silicon film.
摘要翻译：可以通过对由绝缘层隔开的多层电阻多晶硅膜进行构图而在半导体衬底上形成具有减小的空间的电阻梯形网络。这种器件包括形成在半导体衬底上的第一绝缘膜，经由第一绝缘膜形成在设置在半导体衬底上的第一多晶硅膜中的一个或多个串联连接的第一电阻器，设置在第一多晶硅上的第二绝缘膜膜，一个或多个串联连接的第二电阻器，形成在通过第二绝缘膜与第一多晶硅膜分开设置的第二多晶硅膜中，第二多晶硅膜连接到第一多晶硅膜。在第二多晶硅膜上设置第三绝缘膜，通过形成在第三绝缘膜中的接触孔，设置在第二多晶硅膜的表面上的金属线。优选地，第一多晶硅膜比第二多晶硅膜厚，第一多晶硅膜的杂质浓度低于第二多晶硅膜的杂质浓度，第一多晶硅膜的晶粒尺寸较小比第二多晶硅膜的厚度大。

7. 发明授权

US6005275A Semiconductor acceleration sensor with cantilever 失效
标题翻译：具有悬臂的半导体加速度传感器
公开(公告)号：US6005275A
公开(公告)日：1999-12-21
申请号：US518790
申请日：1995-08-23
申请人： Masataka Shinogi , Yutaka Saitoh , Yoshifumi Yoshida , Hirofumi Harada , Kenji Katoh
发明人： Masataka Shinogi , Yutaka Saitoh , Yoshifumi Yoshida , Hirofumi Harada , Kenji Katoh
IPC分类号： G01L1/18 , B81B3/00 , G01L9/00 , G01L9/04 , G01P15/08 , G01P15/12 , G01P15/18 , H01L29/84 , H01L29/82
CPC分类号： G01P15/12 , G01L19/0618 , G01L9/0042 , G01L9/0054 , G01P15/0802 , G01P2015/0828 , Y10S73/01
摘要： A semiconductor device comprises a semiconductor acceleration sensor having a cantilever made of a semiconductor material, a supporter for supporting the cantilever, and diffused resistors disposed on the cantilever. An acceleration detecting device detects a displacement of the cantilever based on acceleration forces applied to the cantilever and on changes of resistance values of the diffused resistors.
摘要翻译：半导体器件包括具有由半导体材料制成的悬臂的半导体加速度传感器，用于支撑悬臂的支撑件和设置在悬臂上的扩散电阻器。加速度检测装置基于施加到悬臂的加速力和扩散电阻器的电阻值的变化来检测悬臂的位移。

8. 发明授权

US09041156B2 Semiconductor reference voltage generating device 有权
标题翻译：半导体参考电压发生装置
公开(公告)号：US09041156B2
公开(公告)日：2015-05-26
申请号：US12584638
申请日：2009-09-09
申请人： Hideo Yoshino , Hirofumi Harada , Jun Osanai
发明人： Hideo Yoshino , Hirofumi Harada , Jun Osanai
IPC分类号： H01L29/78 , G05F3/02 , H01L27/088 , G05F3/24
CPC分类号： H01L27/0883 , G05F3/24
摘要： A reference voltage generating circuit has more than two first wells each having a first impurity concentration and more than two second wells each having a second impurity concentration different from the first impurity concentration. A first group of MOS transistors has more than two MOS transistors formed in respective ones of the first wells. A second group of MOS transistors has More than two MOS transistors formed in respective ones of the second wells.
摘要翻译：参考电压产生电路具有多于两个具有第一杂质浓度的第一阱和多于两个第二阱，每个具有不同于第一杂质浓度的第二杂质浓度。第一组MOS晶体管具有形成在各个第一阱中的两个以上的MOS晶体管。第二组MOS晶体管具有形成在相应的第二阱中的两个以上的MOS晶体管。

9. 发明申请

US20100127334A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
标题翻译：半导体集成电路设备
公开(公告)号：US20100127334A1
公开(公告)日：2010-05-27
申请号：US12613081
申请日：2009-11-05
申请人： Hirofumi Harada
发明人： Hirofumi Harada
IPC分类号： H01L27/088
CPC分类号： H01L21/823892 , H01L27/0207 , H01L27/0928
摘要： Provided is a semiconductor integrated circuit device capable of realizing an analog circuit required to have a high-precision relative ratio between adjacent transistors, which is reduced in size and cost. A single MOS transistor is provided within each of well regions. A plurality of the MOS transistors is combined to serve as an analog circuit block. Since distances between the well regions and channel regions may be made equal to one another, a high-precision semiconductor integrated circuit device can be obtained.
摘要翻译：提供了能够实现相邻晶体管之间具有高精度相对比例所需的模拟电路的半导体集成电路器件，其尺寸和成本降低。在每个阱区域内提供单个MOS晶体管。多个MOS晶体管组合起来用作模拟电路块。由于阱区域和沟道区域之间的距离可以彼此相等，所以可以获得高精度的半导体集成电路器件。

10. 发明申请

US20090152679A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20090152679A1
公开(公告)日：2009-06-18
申请号：US12328207
申请日：2008-12-04
申请人： Hirofumi Harada
发明人： Hirofumi Harada
IPC分类号： H01L29/8605
CPC分类号： H01L29/8605 , H01L27/016 , H01L27/0802 , H01L27/1203
摘要： A metal electrode is disposed on each of a plurality of resistor groups which are made of polycrystalline silicon resistors and constitute a resistor circuit. The metal electrode is connected to an end of the resistor via another interconnecting layer. Accordingly, the external influence which the metal electrode receives during a semiconductor manufacturing process is prevented from directly acting on the resistor, whereby resistance variation is suppressed.
摘要翻译：金属电极设置在由多晶硅电阻器制成并构成电阻电路的多个电阻器组中的每一个上。金属电极通过另一个互连层连接到电阻器的一端。因此，防止了在半导体制造过程中金属电极接收的外部影响直接作用于电阻器，从而抑制了电阻变化。

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