专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06597627B2 Clock switching circuitry for avoiding conflict of data handling occuring in a memory 有权
公开(公告)号：US06597627B2
公开(公告)日：2003-07-22
申请号：US10103844
申请日：2002-03-25
申请人： Yuichi Arata , Naoya Kimura , Hideaki Odagiri
发明人： Yuichi Arata , Naoya Kimura , Hideaki Odagiri
IPC分类号： G11C800
CPC分类号： G11C7/1006 , G11C8/18
摘要： Clock switching circuitry includes a memory having a plurality of storage locations of a particular address each and configured to allow data to be written in and read out at the same time. The circuitry further includes a write pointer, a read pointer, a synchronizing circuit, a conflict detector, and a conflict avoiding circuit. The circuitry detects a conflict with high reliability and facilitates design using a CAD (Computer Aided Design) tool.

2. 发明申请

US20090175255A1 WIRELESS TERMINAL AND BASE STATION DEVICES FOR MULTI-HOP COMMUNICATION 审中-公开
标题翻译：用于多通信通信的无线终端和基站设备
公开(公告)号：US20090175255A1
公开(公告)日：2009-07-09
申请号：US12349603
申请日：2009-01-07
申请人： Hiroyuki AKIYAMA , Hideaki ODAGIRI
发明人： Hiroyuki AKIYAMA , Hideaki ODAGIRI
IPC分类号： H04W88/02
CPC分类号： H04W52/0251 , H04W40/22 , H04W84/12 , Y02D70/142 , Y02D70/22 , Y02D70/39
摘要： A wireless terminal device and a wireless base station device can reduce power consumption required to transmit or receive data in a wireless manner. A frame sent from a wireless LAN terminal station, transfer source, is sent to another wireless LAN terminal station, transfer destination, on a transfer route indicated by routing information stored in a memory to establish a multi-hop communication with a wireless LAN base station.
摘要翻译：无线终端设备和无线基站设备可以以无线方式降低发送或接收数据所需的功耗。从无线LAN终端站传输源发送的帧，在由存储在存储器中的路由信息指示的传送路由上发送到另一无线LAN终端站，传送目的地，以建立与无线LAN基站的多跳通信。

3. 发明授权

US06618280B2 Associative memory for accomplishing longest coincidence data detection by two comparing operations 失效
公开(公告)号：US06618280B2
公开(公告)日：2003-09-09
申请号：US10142891
申请日：2002-05-13
申请人： Noriaki Takahashi , Hideaki Odagiri
发明人： Noriaki Takahashi , Hideaki Odagiri
IPC分类号： G11C1500
CPC分类号： G11C15/00 , G11C15/04
摘要： An associative memory includes an array of CAM cells each having a transistor indicating a result from comparing a stored bit with a reference bit. The transistors are connected in serial in each row of the array to form a NAND circuit producing a signal representing that the bits stored in all the cells in the row are consistent with the reference bits or otherwise that the cell at the LSB of the row stores a bit consistent with a reference bit. Each column of the array includes a logic circuit for masking the bits except those continuous from the MSB toward the LSB which correspond to the bits of a word having the most bits continuous from the MSB toward the LSB and consistent with the bits of the reference word among the stored words. The NAND circuit in a row of the cells storing a word having the most bits continuous from the MSB toward the LSB and consistent with the corresponding bits of a reference word develops a signal representing the longest coincidence data detected.

4. 发明授权

US06388909B2 Associative memory for accomplishing longest coincidence data detection by two comparing operations 失效
标题翻译：用于通过两个比较操作完成最长的重合数据检测的关联存储器
公开(公告)号：US06388909B2
公开(公告)日：2002-05-14
申请号：US09756212
申请日：2001-01-09
申请人： Noriaki Takahashi , Hideaki Odagiri
发明人： Noriaki Takahashi , Hideaki Odagiri
IPC分类号： G11C1500
CPC分类号： G11C15/00 , G11C15/04
摘要： An associative memory includes an array of CAM cells each having a transistor indicating a result from comparing a stored bit with a reference bit. The transistors are connected in serial in each row of the array to form a NAND circuit producing a signal representing that the bits stored in all the cells in the row are consistent with the reference bits or otherwise that the cell at the LSB of the row stores a bit consistent with a reference bit. Each column of the array includes a logic circuit for masking the bits except those continuous from the MSB toward the LSB which correspond to the bits of a word having the most bits continuous from the MSB toward the LSB and consistent with the bits of the reference word among the stored words. The NAND circuit in a row of the cells storing a word having the most bits continuous from the MSB toward the LSB and consistent with the corresponding bits of a reference word develops a signal representing the longest coincidence data detected.
摘要翻译：关联存储器包括每个具有晶体管的CAM单元阵列，该晶体管表示将存储的比特与参考比较比较的结果。晶体管串联连接在阵列的每一行中以形成NAND电路，产生表示存储在该行中的所有单元中的位与参考位一致的信号，否则存储在该行的LSB的单元存储与参考位有点一致。阵列的每列包括一个逻辑电路，用于屏蔽除了从MSB到LSB的连续位以外的位，这些位对应于具有从MSB到LSB的连续的最多位的字的位，并与参考字的位一致在存储的字中。存储从MSB到LSB最连续的字的单元的一行中的NAND电路与参考字的相应位一致，形成表示检测到的最长一致数据的信号。

5. 发明授权

US06665358B1 Digital matched filter circuit employing analog summation 失效
标题翻译：数字匹配滤波电路采用模拟求和
公开(公告)号：US06665358B1
公开(公告)日：2003-12-16
申请号：US09504495
申请日：2000-02-16
申请人： Hideaki Odagiri
发明人： Hideaki Odagiri
IPC分类号： H04L2706
CPC分类号： H04B1/7093
摘要： A digital matched filter stores a series of values of a digital input signal in a memory, compares each stored value with a corresponding value of a known code, and generates an analog comparison result signal for each comparison. The analog comparison result signals are combined to obtain an analog sum signal, which is then converted to a digital output signal. The digital output signal is obtained in real time, because there is little or no processing delay in combining the analog comparison result signals. The circuits that generate and combine the analog comparison result signals are similar to digital circuits, enabling the digital matched filter to be integrated easily with other digital signal-processing circuits.
摘要翻译：数字匹配滤波器将数字输入信号的一系列值存储在存储器中，将每个存储的值与已知码的对应值进行比较，并且为每个比较生成模拟比较结果信号。模拟比较结果信号被组合以获得模拟和信号，然后将其转换为数字输出信号。数字输出信号是实时获得的，因为在组合模拟比较结果信号时几乎没有或没有处理延迟。产生和组合模拟比较结果信号的电路类似于数字电路，使得数字匹配滤波器能够容易地与其他数字信号处理电路集成。

6. 发明授权

US5905668A Content addressable memory device 失效
标题翻译：内容可寻址存储设备
公开(公告)号：US5905668A
公开(公告)日：1999-05-18
申请号：US958402
申请日：1997-10-29
申请人： Noriaki Takahashi , Hideaki Odagiri , Koji Takeshita , Yuji Uyama
发明人： Noriaki Takahashi , Hideaki Odagiri , Koji Takeshita , Yuji Uyama
IPC分类号： G11C15/04 , G11C15/00
CPC分类号： G11C15/04
摘要： A CAM device has an HIT flag cell and a word select separation circuit, with data being stored in a plurality of CAM cells. The HIT flag cell then stores whether or not data stored in the CAM and inputted words (data) coincide. The word select separation circuit the detects the lowest address values corresponding to words within coinciding words and then sequentially resets HIT flag cells storing the coinciding of words.
摘要翻译： CAM设备具有HIT标志单元和字选择分离电路，数据存储在多个CAM单元中。然后，HIT标志单元存储存储在CAM中的数据和输入的字（数据）是否一致。单词选择分离电路检测与重合字中的单词对应的最低地址值，然后顺序复位存储单词一致的HIT标志单元。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式