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1. 发明申请

US20090224250A1 Top Gate Thin Film Transistor with Enhanced Off Current Suppression 审中-公开
标题翻译：具有增强的关断电流抑制的顶栅薄膜晶体管
公开(公告)号：US20090224250A1
公开(公告)日：2009-09-10
申请号：US12045286
申请日：2008-03-10
申请人： Hidayat Kisdarjono , Apostolos T. Voutsas
发明人： Hidayat Kisdarjono , Apostolos T. Voutsas
IPC分类号： H01L29/786 , H01L21/335
CPC分类号： H01L29/78609 , H01L29/42384 , H01L29/66757
摘要： A bottom-contacted top gate thin film transistor (TFT) with enhanced off current suppression is provided, along with an associated fabrication method. The method provided a substrate. Source and drain regions are formed overlying the substrate, each having a channel interface top surface. A channel is interposed between the source and drain, with contact regions immediately overlying the source/drain (S/D) interface top surfaces. A first dielectric layer is conformally deposited. Then, a second dielectric layer is formed overlying the S/D interface top surfaces, with an opening exposing a portion of the first dielectric overlying the channel. A gate is formed overlying the second dielectric layer and the exposed portion of the first dielectric layer.
摘要翻译：提供了具有增强的关断电流抑制的底部接触的顶栅极薄膜晶体管（TFT）以及相关的制造方法。该方法提供了基底。源极和漏极区域形成在衬底上，每个衬底具有沟道界面顶表面。沟道介于源极和漏极之间，接触区域立即覆盖源极/漏极（S / D）界面顶部表面。第一电介质层被共形沉积。然后，在S / D接口顶表面上形成第二电介质层，其中开口暴露第一电介质覆盖通道的一部分。形成覆盖第二电介质层和第一介电层的暴露部分的栅极。

2. 发明授权

US07872309B2 Self-aligned lightly doped drain recessed-gate thin-film transistor 有权
标题翻译：自对准轻掺杂漏极栅极薄膜晶体管
公开(公告)号：US07872309B2
公开(公告)日：2011-01-18
申请号：US12140017
申请日：2008-06-16
申请人： Paul J. Schuele , Mark A. Crowder , Apostolos T. Voutsas , Hidayat Kisdarjono
发明人： Paul J. Schuele , Mark A. Crowder , Apostolos T. Voutsas , Hidayat Kisdarjono
IPC分类号： H01L27/12 , H01L29/786
CPC分类号： H01L29/78621 , H01L29/66621 , H01L29/66757 , H01L29/78627
摘要： A recessed-gate thin-film transistor (RG-TFT) with a self-aligned lightly doped drain (LDD) is provided, along with a corresponding fabrication method. The method deposits an insulator overlying a substrate and etches a trench in the insulator. The trench has a bottom and sidewalls. An active silicon (Si) layer is formed overlying the insulator and trench, with a gate oxide layer over the active Si layer. A recessed gate electrode is then formed in the trench. The TFT is doped and LDD regions are formed in the active Si layer overlying the trench sidewalls. The LDD regions have a length that extends from a top of the trench sidewall, to the trench bottom, with a doping density that decreases in response to the LDD length. Alternately stated, the LDD length is directly related to the depth of the trench.
摘要翻译：提供了具有自对准轻掺杂漏极（LDD）的凹入栅极薄膜晶体管（RG-TFT）以及相应的制造方法。该方法沉积覆盖衬底的绝缘体并蚀刻绝缘体中的沟槽。沟槽有一个底部和侧壁。在绝缘体和沟槽上形成有源硅（Si）层，在有源Si层上方形成栅极氧化层。然后在沟槽中形成凹陷栅电极。 TFT是掺杂的，并且LDD区域形成在覆盖沟槽侧壁的有源Si层中。 LDD区域具有从沟槽侧壁的顶部延伸到沟槽底部的长度，其掺杂密度响应于LDD长度而减小。替代地，LDD长度与沟槽的深度直接相关。

3. 发明申请

US20100237355A1 THIN FILM TRANSISTOR, METHOD FOR MANUFACTURING THIN FILM TRANSISTOR, AND DISPLAY DEVICE 审中-公开
标题翻译：薄膜晶体管，制造薄膜晶体管的方法和显示器件
公开(公告)号：US20100237355A1
公开(公告)日：2010-09-23
申请号：US12743059
申请日：2008-11-10
申请人： Masao Moriguchi , Yuichi Saito , Hidayat Kisdarjono
发明人： Masao Moriguchi , Yuichi Saito , Hidayat Kisdarjono
IPC分类号： H01L29/786 , H01L33/16 , H01L21/336
CPC分类号： H01L29/66765 , H01L29/66757 , H01L29/78633 , H01L29/78675 , H01L29/78678
摘要： A thin film transistor with a large on-current and a reduced off-current is provided with high fabrication efficiency.A thin film transistor of the present invention includes a gate electrode; and a microcrystalline silicon layer containing a microcrystalline silicon, the microcrystalline silicon layer having an upper surface and a lower surface which are parallel to a substrate surface and an end surface which extends between the upper surface and the lower surface; first and second contact layers containing impurities which are provided so as to be in contact with the microcrystalline silicon layer; a source electrode which is in contact with the first contact layer; and a drain electrode which is in contact with the second contact layer, wherein at least one of the first and second contact layers is in contact with the microcrystalline silicon layer only at the end surface without being in contact with any of the upper surface and the lower surface.
摘要翻译：提供具有大的导通电流和减小的截止电流的薄膜晶体管具有高制造效率。本发明的薄膜晶体管包括栅电极; 以及包含微晶硅的微晶硅层，所述微晶硅层具有平行于基板表面的上表面和下表面以及在所述上表面和所述下表面之间延伸的端面; 包含杂质的第一和第二接触层设置成与微晶硅层接触; 与所述第一接触层接触的源电极; 以及与第二接触层接触的漏电极，其中第一和第二接触层中的至少一个仅在端面处与微晶硅层接触而不与任何上表面和下表面。

4. 发明授权

US09099718B2 Transition metal hexacyanoferrate battery cathode with single plateau charge/discharge curve 有权
标题翻译：过渡金属hexacyanoferrate电池阴极与单一平台充电/放电曲线
公开(公告)号：US09099718B2
公开(公告)日：2015-08-04
申请号：US13752930
申请日：2013-01-29
申请人： Yuhao Lu , Hidayat Kisdarjono , Jong-Jan Lee , David Evans
发明人： Yuhao Lu , Hidayat Kisdarjono , Jong-Jan Lee , David Evans
IPC分类号： H01M8/02 , H01M4/136 , H02J7/00 , H01M4/58 , H01M10/054 , H01M10/0568 , H01M10/44
CPC分类号： H01M4/5825 , H01M4/136 , H01M4/58 , H01M4/625 , H01M10/054 , H01M10/0568 , H01M10/446 , H01M2004/028 , H02J7/0063 , H02J7/0068 , Y02E60/122
摘要： A transition metal hexacyanoferrate (TMH) cathode battery is provided. The battery has a AxMn[Fe(CN)6]y.zH2O cathode, where the A cations are either alkali or alkaline-earth cations, such as sodium or potassium, where x is in the range of 1 to 2, where y is in the range of 0.5 to 1, and where z is in the range of 0 to 3.5. The AxMn[Fe(CN)6]y.zH2O has a rhombohedral crystal structure with Mn2+/3+ and Fe2+3+ having the same reduction/oxidation potential. The battery also has an electrolyte, and anode made of an A metal, an A composite, or a material that can host A atoms. The battery has a single plateau charging curve, where a single plateau charging curve is defined as a constant charging voltage slope between 15% and 85% battery charge capacity. Fabrication methods are also provided.
摘要翻译：提供了一种过渡金属六氰基铁酸盐（TMH）阴极电池。电池具有AxMn [Fe（CN）6] y.zH 2 O阴极，其中A阳离子是碱金属或碱土金属阳离子，如钠或钾，其中x在1至2的范围内，其中y是在0.5至1的范围内，其中z在0至3.5的范围内。 AxMn [Fe（CN）6] y.zH2O具有具有相同还原/氧化电位的Mn2 + / 3 +和Fe2 + 3 +的菱方晶体结构。电池还具有电解质和由A金属，A复合材料或能够承载A原子的材料制成的阳极。电池具有单个平台充电曲线，其中单个平台充电曲线被定义为电池充电容量的15％至85％之间的恒定充电电压斜率。还提供制造方法。

5. 发明申请

US20080057649A1 Recessed-gate thin-film transistor with self-aligned lightly doped drain 有权
公开(公告)号：US20080057649A1
公开(公告)日：2008-03-06
申请号：US11513977
申请日：2006-08-31
申请人： Paul J. Schuele , Mark A. Crowder , Apostolos T. Voutsas , Hidayat Kisdarjono
发明人： Paul J. Schuele , Mark A. Crowder , Apostolos T. Voutsas , Hidayat Kisdarjono
IPC分类号： H01L21/336
CPC分类号： H01L29/78621 , H01L29/66621 , H01L29/66757 , H01L29/78627
摘要： A recessed-gate thin-film transistor (RG-TFT) with a self-aligned lightly doped drain (LDD) is provided, along with a corresponding fabrication method. The method deposits an insulator overlying a substrate and etches a trench in the insulator. The trench has a bottom and sidewalls. An active silicon (Si) layer is formed overlying the insulator and trench, with a gate oxide layer over the active Si layer. A recessed gate electrode is then formed in the trench. The TFT is doped and LDD regions are formed in the active Si layer overlying the trench sidewalls. The LDD regions have a length that extends from a top of the trench sidewall, to the trench bottom, with a doping density that decreases in response to the LDD length. Alternately stated, the LDD length is directly related to the depth of the trench.

6. 发明申请

US20130257389A1 Supercapacitor with Hexacyanometallate Cathode, Activated Carbone Anode, and Aqueous Electrolyte 有权
标题翻译：超级电容器与六氰基金属阴极，活性炭骨阳极和水电解质
公开(公告)号：US20130257389A1
公开(公告)日：2013-10-03
申请号：US13603322
申请日：2012-09-04
申请人： Yuhao Lu , Sean Andrew Vail , Hidayat Kisdarjono , Jong-Jan Lee
发明人： Yuhao Lu , Sean Andrew Vail , Hidayat Kisdarjono , Jong-Jan Lee
IPC分类号： H01G9/155 , H01G9/00 , H02J7/00
CPC分类号： H01G11/30 , Y02E60/13 , Y10T29/417
摘要： A supercapacitor is provided with a method for fabricating the supercapacitor. The method provides dried hexacyanometallate particles having a chemical formula AmM1xM2y(CN)6.pH2O with a Prussian Blue hexacyanometallate, crystal structure, where A is an alkali or alkaline-earth cation, and M1 and M2 are metals with 2+ or 3+ valance positions. The variable m is in the range of 0.5 to 2, x is in the range of 0.5 to 1.5, y is in the range of 0.5 to 1.5, and p is in the range of 0 to 6. The hexacyanometallate particles are mixed with a binder and electronic conductor powder, to form a cathode comprising AmM1xM2y(CN)6.pH2O. The method also forms an activated carbon anode and a membrane separating the cathode from the anode, permeable to A and A′ cations. Finally, an electrolyte is added with a metal salt including A′ cations. The electrolyte may be aqueous.
摘要翻译：超级电容器具有制造超级电容器的方法。该方法提供具有化学式AmM1xM2y（CN）6.pH2O的干燥的六氰基金属盐颗粒与普鲁士蓝六氰基金属酸盐晶体结构，其中A是碱金属或碱土金属阳离子，M1和M2是具有2+或3+价态的金属职位变量m在0.5至2的范围内，x在0.5至1.5的范围内，y在0.5至1.5的范围内，p在0至6的范围内。六氰基金属盐颗粒与粘合剂和电子导体粉末，以形成包含AmM1xM2y（CN )6pH2O的阴极。该方法还形成活性炭阳极和将阴极与阳极分开的膜，其可透过A和A'阳离子。最后，向电解质中加入包含A'阳离子的金属盐。电解质可以是水性的。

7. 发明申请

US20080246088A1 Self-Aligned Lightly Doped Drain Recessed-Gate Thin-Film Transistor 有权
标题翻译：自对准轻掺杂漏极栅极薄膜晶体管
公开(公告)号：US20080246088A1
公开(公告)日：2008-10-09
申请号：US12140017
申请日：2008-06-16
申请人： Paul j. Schuele , Mark A. Crowder , Apostolos T. Voutsas , Hidayat Kisdarjono
发明人： Paul j. Schuele , Mark A. Crowder , Apostolos T. Voutsas , Hidayat Kisdarjono
IPC分类号： H01L29/786
CPC分类号： H01L29/78621 , H01L29/66621 , H01L29/66757 , H01L29/78627
摘要： A recessed-gate thin-film transistor (RG-TFT) with a self-aligned lightly doped drain (LDD) is provided, along with a corresponding fabrication method. The method deposits an insulator overlying a substrate and etches a trench in the insulator. The trench has a bottom and sidewalls. An active silicon (Si) layer is formed overlying the insulator and trench, with a gate oxide layer over the active Si layer. A recessed gate electrode is then formed in the trench. The TFT is doped and LDD regions are formed in the active Si layer overlying the trench sidewalls. The LDD regions have a length that extends from a top of the trench sidewall, to the trench bottom, with a doping density that decreases in response to the LDD length. Alternately stated, the LDD length is directly related to the depth of the trench.
摘要翻译：提供了具有自对准轻掺杂漏极（LDD）的凹入栅极薄膜晶体管（RG-TFT）以及相应的制造方法。该方法沉积覆盖衬底的绝缘体并蚀刻绝缘体中的沟槽。沟槽有一个底部和侧壁。在绝缘体和沟槽上形成有源硅（Si）层，在有源Si层上方形成栅极氧化层。然后在沟槽中形成凹陷栅电极。 TFT是掺杂的，并且LDD区域形成在覆盖沟槽侧壁的有源Si层中。 LDD区域具有从沟槽侧壁的顶部延伸到沟槽底部的长度，其掺杂密度响应于LDD长度而减小。替代地，LDD长度与沟槽的深度直接相关。

8. 发明授权

US07419858B2 Recessed-gate thin-film transistor with self-aligned lightly doped drain 有权
标题翻译：具有自对准轻掺杂漏极的嵌入式栅极薄膜晶体管
公开(公告)号：US07419858B2
公开(公告)日：2008-09-02
申请号：US11513977
申请日：2006-08-31
申请人： Paul J. Schuele , Mark A. Crowder , Apostolos T. Voutsas , Hidayat Kisdarjono
发明人： Paul J. Schuele , Mark A. Crowder , Apostolos T. Voutsas , Hidayat Kisdarjono
IPC分类号： H01L21/84
CPC分类号： H01L29/78621 , H01L29/66621 , H01L29/66757 , H01L29/78627
摘要： A recessed-gate thin-film transistor (RG-TFT) with a self-aligned lightly doped drain (LDD) is provided, along with a corresponding fabrication method. The method deposits an insulator overlying a substrate and etches a trench in the insulator. The trench has a bottom and sidewalls. An active silicon (Si) layer is formed overlying the insulator and trench, with a gate oxide layer over the active Si layer. A recessed gate electrode is then formed in the trench. The TFT is doped and LDD regions are formed in the active Si layer overlying the trench sidewalls. The LDD regions have a length that extends from a top of the trench sidewall, to the trench bottom, with a doping density that decreases in response to the LDD length. Alternately stated, the LDD length is directly related to the depth of the trench.
摘要翻译：提供了具有自对准轻掺杂漏极（LDD）的凹入栅极薄膜晶体管（RG-TFT）以及相应的制造方法。该方法沉积覆盖衬底的绝缘体并蚀刻绝缘体中的沟槽。沟槽有一个底部和侧壁。在绝缘体和沟槽上形成有源硅（Si）层，在有源Si层上方形成栅极氧化层。然后在沟槽中形成凹陷栅电极。 TFT是掺杂的，并且LDD区域形成在覆盖沟槽侧壁的有源Si层中。 LDD区域具有从沟槽侧壁的顶部延伸到沟槽底部的长度，其掺杂密度响应于LDD长度而减小。替代地，LDD长度与沟槽的深度直接相关。

9. 发明授权

US09159502B2 Supercapacitor with hexacyanometallate cathode, activated carbon anode, and non-aqueous electrolyte 有权
标题翻译：具有六金属金属阴极，活性炭阳极和非水电解质的超级电容器
公开(公告)号：US09159502B2
公开(公告)日：2015-10-13
申请号：US13603322
申请日：2012-09-04
申请人： Yuhao Lu , Sean Andrew Vail , Hidayat Kisdarjono , Jong-Jan Lee
发明人： Yuhao Lu , Sean Andrew Vail , Hidayat Kisdarjono , Jong-Jan Lee
IPC分类号： H01M2/16 , H01G11/30
CPC分类号： H01G11/30 , Y02E60/13 , Y10T29/417
摘要： A supercapacitor is provided with a method for fabricating the supercapacitor. The method provides dried hexacyanometallate particles having a chemical formula AmM1xM2y(CN)6.pH2O with a Prussian Blue hexacyanometallate, crystal structure, where A is an alkali or alkaline-earth cation, and M1 and M2 are metals with 2+ or 3+ valance positions. The variable m is in the range of 0.5 to 2, x is in the range of 0.5 to 1.5, y is in the range of 0.5 to 1.5, and p is in the range of 0 to 6. The hexacyanometallate particles are mixed with a binder and electronic conductor powder, to form a cathode comprising AmM1xM2y(CN)6.pH2O. The method also forms an activated carbon anode and a membrane separating the cathode from the anode, permeable to A and A′ cations. Finally, an electrolyte is added with a metal salt including A′ cations. The electrolyte may be aqueous.
摘要翻译：超级电容器具有制造超级电容器的方法。该方法提供具有化学式AmM1xM2y（CN）6.pH2O的干燥的六氰基金属盐颗粒与普鲁士蓝六氰基金属酸盐晶体结构，其中A是碱金属或碱土金属阳离子，M1和M2是具有2+或3+价态的金属职位变量m在0.5至2的范围内，x在0.5至1.5的范围内，y在0.5至1.5的范围内，p在0至6的范围内。六氰基金属盐颗粒与粘合剂和电子导体粉末，以形成包含AmM1xM2y（CN )6pH2O的阴极。该方法还形成活性炭阳极和将阴极与阳极分开的膜，其可透过A和A'阳离子。最后，向电解质中加入包含A'阳离子的金属盐。电解质可以是水性的。

10. 发明授权

US08896065B2 Top gate thin film transistor with independent field control for off-current suppression 有权
标题翻译：顶栅薄膜晶体管，具有独立的场控制，用于截止电流抑制
公开(公告)号：US08896065B2
公开(公告)日：2014-11-25
申请号：US12102770
申请日：2008-04-14
申请人： Hidayat Kisdarjono , Apostolos T. Voutsas
发明人： Hidayat Kisdarjono , Apostolos T. Voutsas
IPC分类号： H01L29/786 , H01L29/423
CPC分类号： H01L29/78609 , H01L29/42384 , H01L29/78645 , H01L29/78696
摘要： A bottom-contacted top gate (TG) thin film transistor (TFT) with independent field control for off-current suppression is provided, along with an associated fabrication method. The method provides a substrate, and forms source and drain regions overlying the substrate, each having a channel interface top surface. A channel is interposed between the source and drain, with source and drain contact regions immediately overlying the source/drain (S/D) interface top surfaces, respectively. A first dielectric layer is formed overlying the source, drain, and channel. A first gate is formed overlying the first dielectric, having a drain sidewall located between the contact regions. A second dielectric layer is formed overlying the first gate and first dielectric. A second gate overlies the second dielectric, located over the drain contact region.
摘要翻译：提供了具有用于截止电流抑制的独立场控制的底接触顶栅（TG）薄膜晶体管（TFT），以及相关的制造方法。该方法提供衬底，并且形成覆盖衬底的源极和漏极区域，每个具有通道界面顶表面。沟道介于源极和漏极之间，源极和漏极接触区域分别紧贴在源极/漏极（S / D）界面顶部表面上。在源极，漏极和沟道上形成第一介电层。形成第一栅极覆盖第一电介质，其具有位于接触区域之间的漏极侧壁。第二电介质层形成在第一栅极和第一电介质上。第二栅极覆盖位于漏极接触区域上方的第二电介质。

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