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    • 1. 发明授权
    • Display panel and display apparatus having the same
    • 显示面板和具有该显示面板的显示装置
    • US08558776B2
    • 2013-10-15
    • US11999329
    • 2007-12-04
    • Min-Cheol LeeHee-Bum ParkYong-Soon LeeSeung-Soo BaekSang-Jin Jeon
    • Min-Cheol LeeHee-Bum ParkYong-Soon LeeSeung-Soo BaekSang-Jin Jeon
    • G09G3/36
    • G09G3/3611G09G3/3677G09G2320/0223
    • In a display panel and a display apparatus having the display panel, the display panel includes array and opposite substrates. The array substrate includes display and peripheral areas. Gate and source lines are formed in the display area. A gate driving part and first and second clock lines are formed in the peripheral area. The gate driving part outputs gate signals to the gate line. The first and second clock lines respectively transmit first and second clock signals to the gate driving part. The opposite substrate is combined with the array substrate and includes a common electrode layer. The common electrode layer has an opening portion patterned to expose the first and second clock lines. The exposed portions of the first and second clock lines have substantially the same area. Thus, delays of the gate signals may be minimized and distortion of the gate signals may be prevented.
    • 在具有显示面板的显示面板和显示装置中,显示面板包括阵列和相对的基板。 阵列基板包括显示器和外围区域。 栅极和源极线形成在显示区域中。 在周边区域中形成栅极驱动部分和第一和第二时钟线。 栅极驱动部分将栅极信号输出到栅极线。 第一和第二时钟线分别将第一和第二时钟信号发送到门驱动部分。 相对的衬底与阵列衬底组合并且包括公共电极层。 公共电极层具有图案化以暴露第一和第二时钟线的开口部分。 第一和第二时钟线的暴露部分具有基本上相同的面积。 因此,可以使门信号的延迟最小化并且可以防止门信号的失真。
    • 5. 发明申请
    • Display panel and display apparatus having the same
    • 显示面板和具有该显示面板的显示装置
    • US20080129717A1
    • 2008-06-05
    • US11999329
    • 2007-12-04
    • Min-Cheol LeeHee-Bum ParkYong-Soon LeeSeung-Soo BaekSang-jin Jeon
    • Min-Cheol LeeHee-Bum ParkYong-Soon LeeSeung-Soo BaekSang-jin Jeon
    • G06F3/038
    • G09G3/3611G09G3/3677G09G2320/0223
    • In a display panel and a display apparatus having the display panel, the display panel includes array and opposite substrates. The array substrate includes display and peripheral areas. Gate and source lines are formed in the display area. A gate driving part and first and second clock lines are formed in the peripheral area. The gate driving part outputs gate signals to the gate line. The first and second clock lines respectively transmit first and second clock signals to the gate driving part. The opposite substrate is combined with the array substrate and includes a common electrode layer. The common electrode layer has an opening portion patterned to expose the first and second clock lines. The exposed portions of the first and second clock lines have substantially the same area. Thus, delays of the gate signals may be minimized and distortion of the gate signals may be prevented.
    • 在具有显示面板的显示面板和显示装置中,显示面板包括阵列和相对的基板。 阵列基板包括显示器和外围区域。 栅极和源极线形成在显示区域中。 在周边区域中形成栅极驱动部分和第一和第二时钟线。 栅极驱动部分将栅极信号输出到栅极线。 第一和第二时钟线分别将第一和第二时钟信号发送到门驱动部分。 相对的衬底与阵列衬底组合并且包括公共电极层。 公共电极层具有图案化以暴露第一和第二时钟线的开口部分。 第一和第二时钟线的暴露部分具有基本上相同的面积。 因此,可以使门信号的延迟最小化并且可以防止门信号的失真。