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    • 1. 发明申请
    • Methods and Systems for Detection Using Threshold-Type Electrostatic Sensors
    • 使用阈值型静电传感器进行检测的方法和系统
    • US20100321027A1
    • 2010-12-23
    • US12791293
    • 2010-06-01
    • Mahmoud Elsayed KhaterEihab Mohamed Abdel-RahmanAli Hasan Nayfeh
    • Mahmoud Elsayed KhaterEihab Mohamed Abdel-RahmanAli Hasan Nayfeh
    • G01N27/60G01R19/04
    • G01G3/00B81B2203/0118B81C99/003G01N27/61
    • Methods, apparatus and systems are described as relating to electrostatic sensors for detection in micro or nano electromechanical systems. In exemplary embodiments, a sensor for detecting a threshold value of is provided. The sensor includes a deformable member with a mass detection area, an electrostatic actuator having first and second plates, the first plate being connected to the mass detection area, and a voltage source connected to each of the first and second plate. The operating voltage being proximate to a local bifurcation point of the electrostatic sensor for the first and second plates to pull-in together. Upon an external mass having the threshold value appearing on the mass detection area, the local bifurcation point of the electrostatic sensor is shifted such that the first and second plates will pull in to contact each other by movement of the deformable member to signal detection.
    • 方法,装置和系统被描述为涉及用于在微机械或纳米机电系统中检测的静电传感器。 在示例性实施例中,提供了用于检测阈值的传感器。 传感器包括具有质量检测区域的可变形构件,具有第一和第二板的静电致动器,第一板连接到质量检测区域,以及电压源,连接到第一和第二板中的每一个。 工作电压靠近静电传感器的局部分叉点,以使第一和第二板一起拉入。 当出现在质量检测区域上的具有阈值的外部质量时,静电传感器的局部分叉点被移动,使得第一和第二板通过可变形构件的移动而被拉入以相互接触以进行信号检测。
    • 3. 发明申请
    • STRUCTURE AND METHOD FOR REDUCING MILLER CAPACITANCE IN FIELD EFFECT TRANSISTORS
    • 用于降低场效应晶体管中的MILLER电容的结构和方法
    • US20070117334A1
    • 2007-05-24
    • US11164343
    • 2005-11-18
    • Hasan NayfehAndrew Waite
    • Hasan NayfehAndrew Waite
    • H01L21/336H01L29/76
    • H01L29/78639H01L29/458H01L29/66772
    • A method for forming a field effect transistor (FET) device includes forming a gate conductor and gate dielectric on an active device area of a semiconductor wafer, the semiconductor wafer including a buried insulator layer formed over a bulk substrate and a semiconductor-on-insulator layer initially formed over the buried insulator layer. Source and drain extensions are formed in the semiconductor-on-insulator layer, adjacent opposing sides of the gate conductor, and source and drain sidewall spacers are formed adjacent the gate conductor. Remaining portions of the semiconductor-on-insulator layer adjacent the sidewall spacers and are removed so as to expose portions of the buried insulator layer. The exposed portions of the buried insulator layer are removed so as to expose portions of the bulk substrate. A semiconductor layer is epitaxially grown on the exposed portions of the bulk substrate and the source and drain extensions, and source and drain implants are formed in the epitaxially grown layer.
    • 一种用于形成场效应晶体管(FET)器件的方法包括在半导体晶片的有源器件区域上形成栅极导体和栅极电介质,所述半导体晶片包括形成于体基板上的掩埋绝缘体层和绝缘体上半导体 层最初形成在掩埋绝缘体层上。 源极和漏极延伸部分形成在绝缘体上半导体层中,栅极导体的相邻相对侧,源极和漏极侧壁间隔物邻近栅极导体形成。 绝缘体上半导体层的邻近侧壁间隔物的剩余部分被去除,以便露出掩埋绝缘体层的部分。 去除掩埋绝缘体层的暴露部分以暴露本体衬底的部分。 外延生长在体基板和源极和漏极延伸部分的暴露部分上的半导体层,并且在外延生长层中形成源极和漏极注入。