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    • 7. 发明申请
    • CURRENT INTEGRATOR WITH WIDE DYNAMIC RANGE
    • 具有宽动态范围的电流积分器
    • US20100253321A1
    • 2010-10-07
    • US12741042
    • 2008-10-31
    • Jacobus Josephus LeijssenHarry Marinus
    • Jacobus Josephus LeijssenHarry Marinus
    • G01R17/02
    • G01R19/0092G01N21/4795G01R19/0023G01R19/0061G01R19/16566
    • The invention relates to a determination circuit for measuring a current. The invention also relates to a method for measuring a current using such a determination circuit and to a computer program product adapted, when being executed by a processor, to integrate a current using such a determination circuit. According to the invention an integration circuit comprising the determination circuit is reset each time the integration value of the current exceeds the threshold until expiration of a predefined maximum integration time. The invention increases the accuracy of integrating a current and also increases the dynamic range of currents that can be integrated. To further increase the dynamic range of currents as can be integrated the determination circuit may comprise circuits having different gain factors.
    • 本发明涉及一种用于测量电流的确定电路。 本发明还涉及一种使用这种确定电路和计算机程序产品测量电流的方法,该计算机程序产品在由处理器执行时使用这种确定电路来集成电流。 根据本发明,每当电流的积分值超过阈值直到预定的最大积分时间到期时,包括确定电路的积分电路被复位。 本发明提高了积分电流的精度,并且还增加了可以集成的电流的动态范围。 为了进一步增加可以积分的电流的动态范围,确定电路可以包括具有不同增益因子的电路。
    • 10. 发明授权
    • Reset and watchdog system for a microprocessor, and appliance comprising
microprocessor and such a system
    • 用于微处理器的复位和看门狗系统,以及包括微处理器和这种系统的器具
    • US5674422A
    • 1997-10-07
    • US417291
    • 1995-04-05
    • Harry Marinus
    • Harry Marinus
    • G06F1/28G06F1/24G06F11/00G06F11/30H05B1/02
    • G06F11/0757
    • A system comprising a microprocessor and a reset and watchdog circuit. The microprocessor generates a first pulse train (P1) to indicate the correct operation of the microprocessor and the reset and watchdog circuit generates a reset signal (RST) in response to an irregularity in the occurrence of the first pulse train. The first pulse train is a substantially synchronous software copy of a second pulse train (P2) which is received by the microprocessor and which is preferably a limited a.c. supply voltage signal. This copy is generated by an appropriate programming of the microprocessor. The reset and watchdog circuit receives the first pulse train (P1) and the second pulse train (P2) and supplies the reset signal (RST) in response to a disturbed synchronism between the occurrence of the first pulse train and the second pulse train.
    • 一种包括微处理器和复位和看门狗电路的系统。 微处理器产生第一脉冲串(P1)以指示微处理器的正确操作,并且复位和看门狗电路响应于第一脉冲串发生的不规则性而产生复位信号(RST)。 第一脉冲串是由微处理器接收的第二脉冲串(P2)的基本上同步的软件副本,并且优选地是一个有限的直流。 电源电压信号。 该副本由微处理器的适当编程产生。 复位和看门狗电路接收第一脉冲串(P1)和第二脉冲串(P2),并响应于第一脉冲串和第二脉冲串的发生之间的干扰同步而提供复位信号(RST)。