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1. 发明授权

US08112697B2 Method and apparatus for buffering an encoded signal for a turbo decoder 有权
标题翻译：用于缓冲turbo解码器的编码信号的方法和装置
公开(公告)号：US08112697B2
公开(公告)日：2012-02-07
申请号：US12004569
申请日：2007-12-21
申请人： Amit Anand , Hariprasad Gangadharan , Prasoon Kumar
发明人： Amit Anand , Hariprasad Gangadharan , Prasoon Kumar
IPC分类号： H03M13/03 , H03M13/00 , G06F11/00 , H04B10/08
CPC分类号： H03M13/2957 , H03M13/6362 , H03M13/6544 , H04L1/005 , H04L1/0066 , H04L1/0068 , H04L1/0071
摘要： A method and apparatus for buffering an encoded signal having a plurality of codewords for a turbo decoder is provided. The method comprises de-interleaving each sub-block of the codeword received at the turbo-decoder; and storing LLRs of the de-interleaved codeword LLRs into an input buffer. Thereafter, each of punctured locations, if any, in the de-interleaved codeword is indicated to a read logic for enabling the latter to fill in each of those locations with a pre-determined LLR value as and when a read request corresponding to one of those locations arrives. This method obviates the need for storing the pre-determined LLRs at the punctured locations into the input buffer and thereby cuts down the input latency of turbo decoder significantly for higher code rates.
摘要翻译：提供一种用于缓冲具有用于turbo解码器的多个码字的编码信号的方法和装置。该方法包括对在turbo解码器处接收到的码字的每个子块进行解交织; 并将解交织的码字LLR的LLR存储到输入缓冲器中。此后，解交织的码字中的每个穿孔位置（如果有的话）被指示给读取逻辑，以使后者能够以预定的LLR值填充这些位置中的每一个，并且当对应于那些地点到达。该方法避免了将穿孔位置处的预定LLR存储到输入缓冲器中，从而显着降低turbo解码器的输入等待时间以达到更高码率的需要。

2. 发明申请

US20130130751A1 WIRELESS COMMUNICATION DEVICE HAVING REDUCED POWER CONSUMPTION 有权
标题翻译：具有降低功耗的无线通信设备
公开(公告)号：US20130130751A1
公开(公告)日：2013-05-23
申请号：US13309290
申请日：2011-12-01
申请人： Shashidhar Vummintala , Gowrisankar Somichetty , Sriram Rajagopal , Sindhu Verma , Manish Airy , Hariprasad Gangadharan , Pugazhanthi R.P. , Felix Varghese , Erik Stauffer
发明人： Shashidhar Vummintala , Gowrisankar Somichetty , Sriram Rajagopal , Sindhu Verma , Manish Airy , Hariprasad Gangadharan , Pugazhanthi R.P. , Felix Varghese , Erik Stauffer
IPC分类号： H04W52/02
CPC分类号： H04W52/0216 , H03D7/16 , H04L41/0803 , H04W28/0263 , Y02D70/00 , Y02D70/1262 , Y02D70/146 , Y02D70/164 , Y02D70/23 , Y02D70/24
摘要： A wireless communication device is disclosed that is capable of reduced power consumption. Uplink and downlink sub-frames in a WiMAX, 802.16m or LTE environment often include several vacant symbols during which power-hungry hardware and software components need not operate at full power. By analyzing a physical layer beacon and control information of a received signal, the specific locations of data bursts can be determined, as well as periods of needed operation of a receiver module to effectively decode those data bursts. The receiver module can otherwise be controlled to operate in a LOW power state during remaining periods of vacant time, thereby conserving power consumption and extending battery life.
摘要翻译：公开了能够降低功耗的无线通信设备。 WiMAX，802.16m或LTE环境中的上行链路和下行链路子帧通常包括几个空闲符号，在此期间，功耗很大的硬件和软件组件不需要在全功率下运行。通过分析接收信号的物理层信标和控制信息，可以确定数据突发的特定位置以及接收机模块有效解码这些数据脉冲串的所需操作周期。否则，在空闲时间的剩余时间期间，接收器模块可以被控制为在低功率状态下操作，从而节省功耗并延长电池寿命。

3. 发明授权

US09008734B2 Wireless communication device having reduced power consumption 有权
标题翻译：无线通信设备具有降低的功耗
公开(公告)号：US09008734B2
公开(公告)日：2015-04-14
申请号：US13309290
申请日：2011-12-01
申请人： Shashidhar Vummintala , Gowrisankar Somichetty , Sriram Rajagopal , Sindhu Verma , Manish Airy , Hariprasad Gangadharan , Ramasamy Palanisamy Pugazhanthi , Felix Varghese , Erik Stauffer
发明人： Shashidhar Vummintala , Gowrisankar Somichetty , Sriram Rajagopal , Sindhu Verma , Manish Airy , Hariprasad Gangadharan , Ramasamy Palanisamy Pugazhanthi , Felix Varghese , Erik Stauffer
IPC分类号： H04B1/00 , H04W4/00 , H04W52/02
CPC分类号： H04W52/0216 , H03D7/16 , H04L41/0803 , H04W28/0263 , Y02D70/00 , Y02D70/1262 , Y02D70/146 , Y02D70/164 , Y02D70/23 , Y02D70/24
摘要： A wireless communication device is disclosed that is capable of reduced power consumption. Uplink and downlink sub-frames in a WiMAX, 802.16m or LTE environment often include several vacant symbols during which power-hungry hardware and software components need not operate at full power. By analyzing a physical layer beacon and control information of a received signal, the specific locations of data bursts can be determined, as well as periods of needed operation of a receiver module to effectively decode those data bursts. The receiver module can otherwise be controlled to operate in a LOW power state during remaining periods of vacant time, thereby conserving power consumption and extending battery life.
摘要翻译：公开了能够降低功耗的无线通信设备。 WiMAX，802.16m或LTE环境中的上行链路和下行链路子帧通常包括几个空闲符号，在此期间，功耗很大的硬件和软件组件不需要在全功率下运行。通过分析接收信号的物理层信标和控制信息，可以确定数据突发的特定位置以及接收机模块有效解码这些数据脉冲串的所需操作周期。否则，在空闲时间的剩余时间期间，接收器模块可以被控制为在低功率状态下操作，从而节省功耗并延长电池寿命。

4. 发明申请

US20090164868A1 Method and apparatus for buffering an encoded signal for a turbo decoder 有权
标题翻译：用于缓冲turbo解码器的编码信号的方法和装置
公开(公告)号：US20090164868A1
公开(公告)日：2009-06-25
申请号：US12004569
申请日：2007-12-21
申请人： Amit Anand , Hariprasad Gangadharan , Prasoon Kumar
发明人： Amit Anand , Hariprasad Gangadharan , Prasoon Kumar
IPC分类号： G06F11/10 , H03M13/00
CPC分类号： H03M13/2957 , H03M13/6362 , H03M13/6544 , H04L1/005 , H04L1/0066 , H04L1/0068 , H04L1/0071
摘要： A method and apparatus for buffering an encoded signal having a plurality of codewords for a turbo decoder is provided. The method comprises de-interleaving each sub-block of the codeword received at the turbo-decoder; and storing LLRs of the de-interleaved codeword LLRs into an input buffer. Thereafter, each of punctured locations, if any, in the de-interleaved codeword is indicated to a read logic for enabling the latter to fill in each of those locations with a pre-determined LLR value as and when a read request corresponding to one of those locations arrives. This method obviates the need for storing the pre-determined LLRs at the punctured locations into the input buffer and thereby cuts down the input latency of turbo decoder significantly for higher code rates.
摘要翻译：提供一种用于缓冲具有用于turbo解码器的多个码字的编码信号的方法和装置。该方法包括对在turbo解码器处接收到的码字的每个子块进行解交织; 并将解交织的码字LLR的LLR存储到输入缓冲器中。此后，解交织的码字中的每个穿孔位置（如果有的话）被指示给读取逻辑，以使后者能够以预定的LLR值填充这些位置中的每一个，并且当对应于那些地点到达。该方法避免了将穿孔位置处的预定LLR存储到输入缓冲器中，从而显着降低turbo解码器的输入等待时间以达到更高码率的需要。

5. 发明授权

US07324562B1 Method and apparatus for introducing differential delay between virtually concatenated tributaries 有权
标题翻译：在虚拟连接的支流之间引入差分延迟的方法和装置
公开(公告)号：US07324562B1
公开(公告)日：2008-01-29
申请号：US10327250
申请日：2002-12-20
申请人： Subramani Shankar , Velamur Krishnamachari Vasudevan , Ponnusamy Kanagaralu , Hariprasad Gangadharan
发明人： Subramani Shankar , Velamur Krishnamachari Vasudevan , Ponnusamy Kanagaralu , Hariprasad Gangadharan
IPC分类号： H04J3/06
CPC分类号： H04J3/14 , H04J2203/0062 , H04J2203/0094 , Y10S370/907
摘要： In one embodiment, the invention is an apparatus for testing differential delay correction of network elements using virtual concatenation. The apparatus includes a first PRBS (pseudo-random bit stream) generator dedicated to a first tributary. The apparatus also includes an interface between the first PRBS generator and a tester. The apparatus further includes an interface between the first PRBS generator and a device under test. The apparatus may further include a second PRBS dedicated to a second tributary. The apparatus may also include a control logic block to control the first PRBS generator and the second PRBS generator, and coupled to the first PRBS generator and the second PRBS generator.
摘要翻译：在一个实施例中，本发明是一种用于使用虚拟级联来测试网络元件的差分延迟校正的装置。该装置包括专用于第一支流的第一PRBS（伪随机比特流）生成器。该装置还包括第一PRBS发生器和测试器之间的接口。该装置还包括在第一PRBS发生器和被测器件之间的接口。该装置还可以包括专用于第二支流的第二PRBS。该装置还可以包括用于控制第一PRBS发生器和第二PRBS发生器并且耦合到第一PRBS发生器和第二PRBS发生器的控制逻辑块。

6. 发明授权

US07493392B1 Method and apparatus for assembly of virtually concatenated data 失效
标题翻译：用于组装虚拟级联数据的方法和装置
公开(公告)号：US07493392B1
公开(公告)日：2009-02-17
申请号：US10327232
申请日：2002-12-20
申请人： Hariprasad Gangadharan , Madugiri Siddaraju Anitha
发明人： Hariprasad Gangadharan , Madugiri Siddaraju Anitha
IPC分类号： G06F15/173
CPC分类号： H04L49/9094 , H04L49/90 , Y10S707/99942
摘要： In one embodiment, the invention is an apparatus for assembling data for virtual concatenation. The apparatus includes an auxiliary memory having a set of storage locations for data. The apparatus also includes an external memory having a set of storage locations for data. The apparatus further includes a data assembler coupled to the auxiliary memory and the external memory. The data assembler is to read data of a virtual container from the external memory. The data assembler is also to store data of the virtual container in the auxiliary memory. The data assembler is further to determine if all data of the virtual container is present in the auxiliary memory. The data assembler is also to generate a set of addresses of the data of the virtual container in the auxiliary memory. The data assembler is further to read the data of the virtual container from the auxiliary memory. The data assembler is also to interleave the data of the virtual container.
摘要翻译：在一个实施例中，本发明是用于组装虚拟级联的数据的装置。该装置包括具有用于数据的一组存储位置的辅助存储器。该装置还包括具有用于数据的一组存储位置的外部存储器。该装置还包括耦合到辅助存储器和外部存储器的数据组装器。数据汇编器是从外部存储器读取虚拟容器的数据。数据汇编器还将虚拟容器的数据存储在辅助存储器中。数据汇编器进一步确定虚拟容器的所有数据是否存在于辅助存储器中。数据汇编器还用于生成辅助存储器中虚拟容器的数据的一组地址。数据汇编器进一步从辅助存储器读取虚拟容器的数据。数据汇编器还要交织虚拟容器的数据。

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