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1. 发明授权

US3961251A Testing embedded arrays 失效
标题翻译：测试嵌入式阵列
公开(公告)号：US3961251A
公开(公告)日：1976-06-01
申请号：US534605
申请日：1974-12-20
申请人： William J. Hurley , Hans P. Muhlfeld
发明人： William J. Hurley , Hans P. Muhlfeld
IPC分类号： G01R31/3185 , G11C29/48 , G01R15/12
CPC分类号： G01R31/318533 , G11C29/48
摘要： A large scale integrated (LSI) chip or semiconductor device includes a memory array and associated logic circuitry. The array is "embedded" in the sense that it is not directly accessible, either in whole or in part, from the input and output terminals or pads of the device. To facilitate testing there is added to the device gating means to the memory array and wiring extending from primary access points of the device to the memory array bypassing and in parallel with the logic circuitry. The device further includes control means operatively associated with the gating means for switching the input to the array between the logic circuitry and the primary access points. In the latter condition direct access to the array is permitted, thereby facilitating testing.
摘要翻译：大规模集成（LSI）芯片或半导体器件包括存储器阵列和相关联的逻辑电路。该阵列是“嵌入”的，因为它不能从设备的输入和输出端子或焊盘全部或部分直接访问。为了便于测试，添加到设备门控装置到存储器阵列以及从器件的主要接入点延伸到与逻辑电路并联并联的存储器阵列的布线。该装置还包括与门控装置可操作地相关联的控制装置，用于将逻辑电路和主接入点之间的输入切换到阵列。在后一种情况下，允许直接访问阵列，从而便于测试。

2. 发明授权

US4639919A Distributed pattern generator 失效
标题翻译：分布式图案发生器
公开(公告)号：US4639919A
公开(公告)日：1987-01-27
申请号：US564853
申请日：1983-12-19
申请人： Yi-Hua E. Chang , Algirdas J. Gruodis , Hans P. Muhlfeld, Jr. , Charles W. Rodriguez , Mark L. Shulman
发明人： Yi-Hua E. Chang , Algirdas J. Gruodis , Hans P. Muhlfeld, Jr. , Charles W. Rodriguez , Mark L. Shulman
IPC分类号： H01L21/66 , G01R31/3183 , G01R31/319 , G01R31/3193 , G11C29/36 , G11C29/56 , G01R31/28
CPC分类号： G11C29/56 , G01R31/31921 , G01R31/31935 , G11C29/36 , G01R31/31926
摘要： An array testing apparatus includes a plurality of pin pattern generators for individually generating serial bit sequences required at each pin of a device under test during the testing operation. The individual pin pattern generators receive starting addresses from one or more programmable controllers and each pin pattern generator then performs a subroutine to repeat basic patterns or combinations of basic patterns as necessary. Both the pin pattern generators and the programmable controllers may include loop logic for obtaining the desired repetition sequences.
摘要翻译：阵列测试装置包括多个针脚图案发生器，用于在测试操作期间单独地产生在待测器件的每个引脚处所需的串行比特序列。单独的针脚图案发生器从一个或多个可编程控制器接收起始地址，并且每个针脚模式发生器然后执行子程序以根据需要重复基本模式或基本模式的组合。引脚图案发生器和可编程控制器都可以包括用于获得所需重复序列的循环逻辑。

3. 发明授权

US4517661A Programmable chip tester having plural pin unit buffers which each store sufficient test data for independent operations by each pin unit 失效
标题翻译：可编程芯片测试仪具有多个引脚单元缓冲器，每个引脚单元缓冲器每个存储足够的测试数据，用于由每个引脚单元进行独立操作
公开(公告)号：US4517661A
公开(公告)日：1985-05-14
申请号：US283778
申请日：1981-07-16
申请人： Matthew C. Graf , Hans P. Muhlfeld, Jr. , Edward H. Valentine
发明人： Matthew C. Graf , Hans P. Muhlfeld, Jr. , Edward H. Valentine
IPC分类号： G01R31/26 , G01R31/28 , G01R31/319 , H01L21/66 , G06F11/00
CPC分类号： G01R31/31922 , G01R31/31917 , G01R31/31919
摘要： A test system for testing circuits in integrated circuit chips includes a host computer for controlling the test system, and a plurality of blocks operable in parallel and each including a controller, storage for test programs and test data, and plurality of electronic units or pin electronics cards, one unit being associated with one of the pins of a device under test. Each of the electronic units include timing circuitry for timing its associated pin independent of the timing of any other electronics unit.
摘要翻译：用于测试集成电路芯片中的电路的测试系统包括用于控制测试系统的主计算机和并行操作的多个模块，每个模块包括控制器，用于测试程序和测试数据的存储器以及多个电子单元或引脚电子卡，一个单元与被测设备中的一个引脚相关联。每个电子单元包括定时电路，用于定时其相关引脚，独立于任何其它电子单元的定时。

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