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    • 2. 发明申请
    • ARRAY SUBSTRATE AND DRIVING METHOD THEREOF
    • 阵列基板及其驱动方法
    • US20120081415A1
    • 2012-04-05
    • US13242061
    • 2011-09-23
    • Hailin XUEYubo XUCheng LIXiaochuan CHENXin LIShunshun QIU
    • Hailin XUEYubo XUCheng LIXiaochuan CHENXin LIShunshun QIU
    • G09G3/36G02F1/1343G09G5/10
    • G09G3/3685G09G3/3648G09G2310/0205
    • An array substrate is provided comprising a base substrate; an array of pixel electrodes formed on the base substrate; a plurality of gate lines, each of which is formed corresponding to each row of pixel electrodes; a plurality of data lines, each of which is formed corresponding to each odd number column of pixel electrodes and the next adjacent even number column of pixel electrodes; a plurality of first switching devices, each of which is connected with each odd-number-column pixel electrode, and the data lines charging the corresponding odd-number-column pixel electrodes via the corresponding first switching devices under driving control in corresponding time sequence; a plurality of second switching devices, each of which is connected with each even-number-column pixel electrode, and the data lines charging the corresponding even-number-column pixel electrodes via the corresponding second switching devices under driving control in corresponding time sequence.
    • 提供了一种阵列基板,包括基底基板; 形成在基底基板上的像素电极阵列; 多个栅极线,每个栅极线对应于每行像素电极形成; 多个数据线,每个数据线对应于像素电极的每个奇数列和下一个相邻的偶数列列的像素电极; 多个第一开关器件,每个与每个奇数列像素电极连接,数据线通过对应的第一开关器件以相应的时间顺序驱动控制,对相应的奇数列像素电极进行充电; 多个第二开关器件,其每个与每个偶数列像素电极连接,并且数据线在相应的时间顺序的驱动控制下通过相应的第二开关器件对相应的偶数列像素电极进行充电。
    • 4. 发明授权
    • Array substrate and driving method thereof
    • 阵列基板及其驱动方法
    • US08767022B2
    • 2014-07-01
    • US13242061
    • 2011-09-23
    • Hailin XueYubo XuCheng LiXiaochuan ChenXin LiShunshun Qiu
    • Hailin XueYubo XuCheng LiXiaochuan ChenXin LiShunshun Qiu
    • G09G5/10G09G3/36
    • G09G3/3685G09G3/3648G09G2310/0205
    • An array substrate is provided comprising a base substrate; an array of pixel electrodes formed on the base substrate; a plurality of gate lines, each of which is formed corresponding to each row of pixel electrodes; a plurality of data lines, each of which is formed corresponding to each odd number column of pixel electrodes and the next adjacent even number column of pixel electrodes; a plurality of first switching devices, each of which is connected with each odd-number-column pixel electrode, and the data lines charging the corresponding odd-number-column pixel electrodes via the corresponding first switching devices under driving control in corresponding time sequence; a plurality of second switching devices, each of which is connected with each even-number-column pixel electrode, and the data lines charging the corresponding even-number-column pixel electrodes via the corresponding second switching devices under driving control in corresponding time sequence.
    • 提供了一种阵列基板,包括基底基板; 形成在基底基板上的像素电极阵列; 多个栅极线,每个栅极线对应于每行像素电极形成; 多个数据线,每个数据线对应于像素电极的每个奇数列和下一个相邻的偶数列列的像素电极; 多个第一开关器件,每个与每个奇数列像素电极连接,数据线通过对应的第一开关器件以相应的时间顺序驱动控制,对相应的奇数列像素电极进行充电; 多个第二开关器件,其每个与每个偶数列像素电极连接,并且数据线在相应的时间顺序的驱动控制下通过相应的第二开关器件对相应的偶数列像素电极进行充电。
    • 5. 发明申请
    • TFT ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF
    • TFT阵列基板及其制造方法
    • US20120161140A1
    • 2012-06-28
    • US13332689
    • 2011-12-21
    • Hailin XUEYubo XUCheng LIJidong ZHANG
    • Hailin XUEYubo XUCheng LIJidong ZHANG
    • H01L33/08H01L33/62
    • G02F1/136286G02F2201/121H01L27/124
    • An thin film transistor array and a manufacturing method thereof are provided. A thin film transistor (TFT) array substrate comprises a base substrate, horizontal gate lines, reticulated storage capacitor electrode (Vcom) lines, longitudinal data lines defining pixel units with the horizontal gate lines. The Vcom lines corresponding to the pixel units in each row of the reticulated Vcom line are connected with each other, and the reticulated Vcom lines are connected with an integrated-circuit (IC) element through Vcom line IC terminals; if the number of the data lines is N, the number of the Vcom line IC terminals is more than 0 and less than N+1; and at least one Vcom line longitudinal electric connection section is provided between the Vcom lines in two adjacent rows.
    • 提供薄膜晶体管阵列及其制造方法。 薄膜晶体管(TFT)阵列基板包括基底,水平栅极线,网状存储电容电极(Vcom)线,用水平栅极线限定像素单元的纵向数据线。 对应于网状Vcom线的每行中的像素单元的Vcom线彼此连接,网状Vcom线通过Vcom线IC端子与集成电路(IC)元件连接; 如果数据线的数量为N,则Vcom线路IC端子的数量大于0且小于N + 1; 并且在两个相邻行中的Vcom线之间提供至少一个Vcom线纵向电连接部。
    • 6. 发明申请
    • TFT-LCD ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF
    • TFT-LCD阵列基板及其制造方法
    • US20110019117A1
    • 2011-01-27
    • US12840575
    • 2010-07-21
    • Hailin XUEBingqian LINYubo XUCheng LI
    • Hailin XUEBingqian LINYubo XUCheng LI
    • G02F1/136H01L21/336
    • H01L27/124G02F1/13624
    • A thin film transistor liquid crystal display (TFT-LCD) array substrate comprising a first gate line, a second gate line and a data line, which are formed on a substrate and define a pixel region, the first and second gate lines being parallel to each other, a pixel electrode, and a first thin film transistor (TFT) and a second TFT provided in the pixel region. The first TFT comprises a first gate electrode and a first drain electrode, the second TFT comprises a second gate electrode and a second drain electrode, and parasitic capacitance generated between the first drain electrode and the first gate electrode is equal to parasitic capacitance generated between the second drain electrode and the second gate electrode. Both the first drain electrode and the second drain electrode are connected with the pixel electrode. When an “ON” voltage is supplied to the first TFT via the first gate line, a first voltage is supplied to the second TFT via the second gate line; when an “OFF” voltage is supplied to the first TFT via the first gate line, a second voltage is supplied to the second TFT via the second gate line, wherein the “ON” voltage−the “OFF” voltage=the second voltage−the first voltage.
    • 一种薄膜晶体管液晶显示器(TFT-LCD)阵列基板,包括形成在基板上并限定像素区域的第一栅极线,第二栅极线和数据线,所述第一和第二栅极线平行于 彼此,像素电极以及设置在像素区域中的第一薄膜晶体管(TFT)和第二TFT。 第一TFT包括第一栅电极和第一漏电极,第二TFT包括第二栅电极和第二漏电极,并且在第一漏电极和第一栅电极之间产生的寄生电容等于在第 第二漏电极和第二栅电极。 第一漏电极和第二漏电极都与像素电极连接。 当通过第一栅极线向第一TFT提供“ON”电压时,经由第二栅极线将第一电压提供给第二TFT; 当通过第一栅极线向第一TFT提供“OFF”电压时,经由第二栅极线向第二TFT提供第二电压,其中“ON”电压 - “OFF”电压=第二电压 - 第一电压。